Richard Chou

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Cupertino, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Concurrent optimization of 3D-IC with asymmetrical routing layers
- Patent number 11,276,677
- Issue date Mar 15, 2022
- Cadence Design Systems, Inc.
- Liqun Deng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and computer program product for implementing elect...
- Patent number 10,204,180
- Issue date Feb 12, 2019
- Cadence Design Systems, Inc.
- Kai-Ti Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for power gating of an integrated circuit
- Patent number 7,568,177
- Issue date Jul 28, 2009
- Cadence Design Systems, Inc.
- Tobing Soebroto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip power-ground inductance modeling using effective self-loop-...
- Patent number 6,981,230
- Issue date Dec 27, 2005
- Apache Design Solutions, Inc.
- Shen Lin
- G06 - COMPUTING CALCULATING COUNTING