Richard J. STEPHANI

Person

Saint Paul, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for selective write assist using shared boost...
- Patent number 9,959,926
- Issue date May 1, 2018
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Travis R. Hebig
- G11 - INFORMATION STORAGE
Information Patent Grant
High bandwidth memory and glitch-less differential XOR
- Patent number 9,753,667
- Issue date Sep 5, 2017
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Travis Hebig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Content addressable memory data clustering block architecture
- Patent number 8,850,109
- Issue date Sep 30, 2014
- Avago Technologies General IP (Singapore) Pte. Ltd.
- David B. Grover
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Adjusting access times to memory cells based on characterized word-...
- Patent number 8,787,099
- Issue date Jul 22, 2014
- LSI Corporation
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Grant
Adjusting bit-line discharge time in memory arrays based on charact...
- Patent number 8,773,927
- Issue date Jul 8, 2014
- LSI Corporation
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Grant
Segmented memory having power-saving mode
- Patent number 8,773,942
- Issue date Jul 8, 2014
- LSI Corporation
- Richard J. Stephani
- G11 - INFORMATION STORAGE
Information Patent Grant
Split decode latch with shared feedback
- Patent number 8,610,461
- Issue date Dec 17, 2013
- LSI Corporation
- Richard J. Stephani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory device with area efficient power gating circuitry
- Patent number 8,462,562
- Issue date Jun 11, 2013
- LSI Corporation
- Ankur Goel
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power SRAM based content addressable memory
- Patent number 8,264,862
- Issue date Sep 11, 2012
- LSI Corporation
- Richard J. Stephani
- G11 - INFORMATION STORAGE
Information Patent Grant
ROM-based multiple match circuit
- Patent number 7,603,513
- Issue date Oct 13, 2009
- LSI Corporation
- Richard Stephani
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and methods for a static mux-based priority encoder
- Patent number 7,325,092
- Issue date Jan 29, 2008
- LSI Corporation
- Richard J. Stephani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Construction of an optimized SEC-DED code and logic for soft errors...
- Patent number 7,117,420
- Issue date Oct 3, 2006
- LSI Logic Corporation
- Max M. Yeung
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR SELECTIVE WRITE ASSIST
- Publication number 20170117034
- Publication date Apr 27, 2017
- BROADCOM CORPORATION
- Travis R. HEBIG
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH BANDWIDTH MEMORY AND GLITCH-LESS DIFFERENTIAL XOR
- Publication number 20160246506
- Publication date Aug 25, 2016
- BROADCOM CORPORATION
- Travis HEBIG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER HIT BITLINE DRIVER FOR CONTENT-ADDRESSABLE MEMORY
- Publication number 20150262667
- Publication date Sep 17, 2015
- LSI Corporation
- TRAVIS HEBIG
- G11 - INFORMATION STORAGE
Information Patent Application
SEGMENTED MEMORY HAVING POWER-SAVING MODE
- Publication number 20140119147
- Publication date May 1, 2014
- LSI Corporation
- Richard J. Stephani
- G11 - INFORMATION STORAGE
Information Patent Application
ADJUSTING BIT-LINE DISCHARGE TIME IN MEMORY ARRAYS BASED ON CHARACT...
- Publication number 20140071775
- Publication date Mar 13, 2014
- LSI Corporation
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Application
ADJUSTING ACCESS TIMES TO MEMORY CELLS BASED ON CHARACTERIZED WORD-...
- Publication number 20130343139
- Publication date Dec 26, 2013
- LSI Corporation
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Application
LOW POWER CONTENT ADDRESSABLE MEMORY HITLINE PRECHARGE AND SENSING...
- Publication number 20130286705
- Publication date Oct 31, 2013
- David B. Grover
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCING POWER CONSUMPTION OF MEMORY
- Publication number 20130173944
- Publication date Jul 4, 2013
- LSI CORPORATION
- Ross Kohler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTENT ADDRESSABLE MEMORY DATA CLUSTERING BLOCK ARCHITECTURE
- Publication number 20130166850
- Publication date Jun 27, 2013
- David B. Grover
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE WITH AREA EFFICIENT POWER GATING CIRCUITRY
- Publication number 20130128676
- Publication date May 23, 2013
- LSI Corporation
- Ankur Goel
- G11 - INFORMATION STORAGE
Information Patent Application
SPLIT DECODE LATCH WITH SHARED FEEDBACK
- Publication number 20130076393
- Publication date Mar 28, 2013
- Richard J. Stephani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW POWER SRAM BASED CONTENT ADDRESSABLE MEMORY
- Publication number 20120127772
- Publication date May 24, 2012
- Richard J. Stephani
- G11 - INFORMATION STORAGE
Information Patent Application
ROM-Based Multiple Match Circuit
- Publication number 20080086592
- Publication date Apr 10, 2008
- Richard Stephani
- G11 - INFORMATION STORAGE

Richard J. STEPHANI

Person

Patents Grantslast 30 patents

Method and apparatus for selective write assist using shared boost...

High bandwidth memory and glitch-less differential XOR

Content addressable memory data clustering block architecture

Adjusting access times to memory cells based on characterized word-...

Adjusting bit-line discharge time in memory arrays based on charact...

Segmented memory having power-saving mode

Split decode latch with shared feedback

Memory device with area efficient power gating circuitry

Low power SRAM based content addressable memory

ROM-based multiple match circuit

Apparatus and methods for a static mux-based priority encoder

Construction of an optimized SEC-DED code and logic for soft errors...

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR SELECTIVE WRITE ASSIST

HIGH BANDWIDTH MEMORY AND GLITCH-LESS DIFFERENTIAL XOR

LOW POWER HIT BITLINE DRIVER FOR CONTENT-ADDRESSABLE MEMORY

SEGMENTED MEMORY HAVING POWER-SAVING MODE

ADJUSTING BIT-LINE DISCHARGE TIME IN MEMORY ARRAYS BASED ON CHARACT...

ADJUSTING ACCESS TIMES TO MEMORY CELLS BASED ON CHARACTERIZED WORD-...

LOW POWER CONTENT ADDRESSABLE MEMORY HITLINE PRECHARGE AND SENSING...

REDUCING POWER CONSUMPTION OF MEMORY

CONTENT ADDRESSABLE MEMORY DATA CLUSTERING BLOCK ARCHITECTURE

MEMORY DEVICE WITH AREA EFFICIENT POWER GATING CIRCUITRY

SPLIT DECODE LATCH WITH SHARED FEEDBACK

LOW POWER SRAM BASED CONTENT ADDRESSABLE MEMORY

ROM-Based Multiple Match Circuit