Richard Michael PARENT

Person

Shelburne, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Temperature and process driven reference
- Patent number 8,269,550
- Issue date Sep 18, 2012
- Nanya Technology Corp.
- Ryan Andrew Jurasek
- G05 - CONTROLLING REGULATING
Information Patent Grant
Bank re-assignment in chip to reduce IR drop
- Patent number 8,102,690
- Issue date Jan 24, 2012
- Nanya Technology Corp.
- Richard Michael Parent
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM positive wordline voltage compensation device for array device...
- Patent number 7,940,549
- Issue date May 10, 2011
- Nanya Technology Corp.
- Benjamin James Stembridge
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for reducing leakage current of a memory and related device
- Patent number 7,876,612
- Issue date Jan 25, 2011
- Nanya Technology Corp.
- Richard Michael Parent
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for reducing power consumption in a volatile memory and rela...
- Patent number 7,813,209
- Issue date Oct 12, 2010
- Nanya Technology Corp.
- Richard Michael Parent
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual-voltage wordline drive circuit with two stage discharge
- Patent number 7,345,946
- Issue date Mar 18, 2008
- Cypress Semiconductor Corporation
- David Chapman
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier circuit and method of operation
- Patent number 7,330,388
- Issue date Feb 12, 2008
- Cypress Semiconductor Corporation
- David Chapman
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier circuit and method
- Patent number 7,313,041
- Issue date Dec 25, 2007
- Cypress Semiconductor Corporation
- David Chapman
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit for reducing defect current from array element f...
- Patent number 7,095,642
- Issue date Aug 22, 2006
- Cypress Semiconductor Corporation
- Richard Parent
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and architecture for reducing the power consumption for memo...
- Patent number 7,057,960
- Issue date Jun 6, 2006
- Cypress Semiconductor Corp.
- Timothy E. Fiscus
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and architecture for reducing the power consumption for memo...
- Patent number 6,618,314
- Issue date Sep 9, 2003
- Cypress Semiconductor Corp.
- Timothy E. Fiscus
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock system for an embedded semiconductor memory unit
- Patent number 6,396,324
- Issue date May 28, 2002
- International Business Machines Corporation
- Louis L. Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decoded autofresh mode in a DRAM
- Patent number 6,373,769
- Issue date Apr 16, 2002
- Infineon Technologies AG
- Oliver Kiehl
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for preventing noise cross contamination between...
- Patent number 6,349,067
- Issue date Feb 19, 2002
- International Business Machines Corporation
- Louis L. Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Super low-power generator system for embedded applications
- Patent number 6,343,044
- Issue date Jan 29, 2002
- International Business Machines Corporation
- Louis Lu-Chen Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Selective address space refresh mode
- Patent number 6,341,097
- Issue date Jan 22, 2002
- International Business Machines Corporation
- Louis L. Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoded autorefresh mode in a DRAM
- Patent number 6,046,953
- Issue date Apr 4, 2000
- Siemens Aktiengesellschaft
- Oliver Kiehl
- G11 - INFORMATION STORAGE
Information Patent Grant
Weak inversion NMOS regulator with boosted gate
- Patent number 5,998,981
- Issue date Dec 7, 1999
- International Business Machines Corporation
- Russell J. Houghton
- G05 - CONTROLLING REGULATING
Information Patent Grant
Boosted drive system for master/local word line memory architecture
- Patent number 5,255,224
- Issue date Oct 19, 1993
- International Business Machines Corporation
- Duane E. Galbi
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
TEMPERATURE AND PROCESS DRIVEN REFERENCE
- Publication number 20110102057
- Publication date May 5, 2011
- Ryan Andrew Jurasek
- G05 - CONTROLLING REGULATING
Information Patent Application
BANK RE-ASSIGNMENT IN CHIP TO REDUCE IR DROP
- Publication number 20110085402
- Publication date Apr 14, 2011
- Richard Michael Parent
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM POSITIVE WORDLINE VOLTAGE COMPENSATION DEVICE FOR ARRAY DEVICE...
- Publication number 20110080771
- Publication date Apr 7, 2011
- NANYA TECHNOLOGY CORP.
- Benjamin James STEMBRIDGE
- G11 - INFORMATION STORAGE
Information Patent Application
Method for Reducing Leakage Current of a Memory and Related Device
- Publication number 20100085828
- Publication date Apr 8, 2010
- Richard Michael Parent
- G11 - INFORMATION STORAGE
Information Patent Application
Method for Reducing Power Consumption in a Volatile Memory and Rela...
- Publication number 20100080070
- Publication date Apr 1, 2010
- Richard Michael Parent
- G11 - INFORMATION STORAGE

Richard Michael PARENT

Person

Patents Grantslast 30 patents

Temperature and process driven reference

Bank re-assignment in chip to reduce IR drop

DRAM positive wordline voltage compensation device for array device...

Method for reducing leakage current of a memory and related device

Method for reducing power consumption in a volatile memory and rela...

Dual-voltage wordline drive circuit with two stage discharge

Sense amplifier circuit and method of operation

Sense amplifier circuit and method

Method and circuit for reducing defect current from array element f...

Method and architecture for reducing the power consumption for memo...

Method and architecture for reducing the power consumption for memo...

Clock system for an embedded semiconductor memory unit

Decoded autofresh mode in a DRAM

System and method for preventing noise cross contamination between...

Super low-power generator system for embedded applications

Selective address space refresh mode

Decoded autorefresh mode in a DRAM

Weak inversion NMOS regulator with boosted gate

Boosted drive system for master/local word line memory architecture

Patents Applicationslast 30 patents

TEMPERATURE AND PROCESS DRIVEN REFERENCE

BANK RE-ASSIGNMENT IN CHIP TO REDUCE IR DROP

DRAM POSITIVE WORDLINE VOLTAGE COMPENSATION DEVICE FOR ARRAY DEVICE...

Method for Reducing Leakage Current of a Memory and Related Device

Method for Reducing Power Consumption in a Volatile Memory and Rela...