Richard PATERSON

Person

Sheffield, GB

People

Patents Grantslast 30 patents

Information Patent Grant
Method, system and circuit for managing a secure memory partition
- Patent number 11,550,733
- Issue date Jan 10, 2023
- ARM Limited
- Richard Andrew Paterson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit power supply
- Patent number 11,545,976
- Issue date Jan 3, 2023
- ARM Limited
- Richard Andrew Paterson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and/or system for testing devices in non-secured environment
- Patent number 11,480,613
- Issue date Oct 25, 2022
- ARM Limited
- Richard Andrew Paterson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Message handling unit
- Patent number 10,948,963
- Issue date Mar 16, 2021
- ARM Limited
- Richard Andrew Paterson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reset isolation bridge
- Patent number 10,775,862
- Issue date Sep 15, 2020
- ARM Limited
- Richard Andrew Paterson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Correlating local time counts of first and second integrated circuits
- Patent number 10,530,562
- Issue date Jan 7, 2020
- ARM Limited
- Richard Andrew Paterson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for controlling a power supply to processing c...
- Patent number 10,387,234
- Issue date Aug 20, 2019
- ARM Limited
- Richard Paterson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock state control for power saving in an integrated circuit
- Patent number 9,391,614
- Issue date Jul 12, 2016
- ARM Limited
- Richard Paterson
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHOD FOR CONTROLLING ACCESS TO A SHARED RESOURCE
- Publication number 20240241755
- Publication date Jul 18, 2024
- ARM Limited
- Richard Andrew PATERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND/OR SYSTEM FOR TESTING DEVICES IN NON-SECURED ENVIRONMENT
- Publication number 20220196734
- Publication date Jun 23, 2022
- ARM Limited
- Richard Andrew Paterson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD, SYSTEM AND CIRCUIT FOR MANAGING A SECURE MEMORY PARTITION
- Publication number 20220004622
- Publication date Jan 6, 2022
- ARM Limited
- Richard Andrew Paterson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESET ISOLATION BRIDGE
- Publication number 20200192447
- Publication date Jun 18, 2020
- ARM Limited
- Richard Andrew PATERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MESSAGE HANDLING UNIT
- Publication number 20190073011
- Publication date Mar 7, 2019
- ARM Limited
- Richard Andrew PATERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CORRELATING LOCAL TIME COUNTS OF FIRST AND SECOND INTEGRATED CIRCUITS
- Publication number 20180309565
- Publication date Oct 25, 2018
- ARM Limited
- Richard Andrew PATERSON
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
POWER SUPPLY CONTROL
- Publication number 20180039323
- Publication date Feb 8, 2018
- ARM Limited
- Richard PATERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK STATE CONTROL FOR POWER SAVING IN AN INTEGRATED CIRCUIT
- Publication number 20160036440
- Publication date Feb 4, 2016
- ARM Limited
- Richard PATERSON
- H03 - BASIC ELECTRONIC CIRCUITRY

Richard PATERSON

Person

Patents Grantslast 30 patents

Method, system and circuit for managing a secure memory partition

Integrated circuit power supply

Method and/or system for testing devices in non-secured environment

Message handling unit

Reset isolation bridge

Correlating local time counts of first and second integrated circuits

Apparatus and method for controlling a power supply to processing c...

Clock state control for power saving in an integrated circuit

Patents Applicationslast 30 patents

APPARATUS AND METHOD FOR CONTROLLING ACCESS TO A SHARED RESOURCE

METHOD AND/OR SYSTEM FOR TESTING DEVICES IN NON-SECURED ENVIRONMENT

METHOD, SYSTEM AND CIRCUIT FOR MANAGING A SECURE MEMORY PARTITION

RESET ISOLATION BRIDGE

MESSAGE HANDLING UNIT

CORRELATING LOCAL TIME COUNTS OF FIRST AND SECOND INTEGRATED CIRCUITS

POWER SUPPLY CONTROL

CLOCK STATE CONTROL FOR POWER SAVING IN AN INTEGRATED CIRCUIT