Richard Patten

Person

Langquaid, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Package stacking using chip to wafer bonding
- Patent number 11,955,462
- Issue date Apr 9, 2024
- Intel Corporation
- Georg Seidemann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fan out packaging pop mechanical attach method
- Patent number 11,735,570
- Issue date Aug 22, 2023
- Intel Corporation
- David O'Sullivan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic packages with high integration microelectronic dice...
- Patent number 11,527,507
- Issue date Dec 13, 2022
- Intel Corporation
- Richard Patten
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level package structure with internal conductive layer
- Patent number 11,424,209
- Issue date Aug 23, 2022
- Intel Corporation
- Sven Albers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package stacking using chip to wafer bonding
- Patent number 11,239,199
- Issue date Feb 1, 2022
- Intel Corporation
- Georg Seidemann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method, apparatus and system to interconnect packaged integrated ci...
- Patent number 10,910,347
- Issue date Feb 2, 2021
- Intel Corporation
- Yong She
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic packages with high integration microelectronic dice...
- Patent number 10,872,881
- Issue date Dec 22, 2020
- Intel IP Corporation
- Richard Patten
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor die package with more than one hanging die
- Patent number 10,854,590
- Issue date Dec 1, 2020
- Intel IP Corporation
- Sven Albers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packages including an optical redistribution layer
- Patent number 10,816,742
- Issue date Oct 27, 2020
- Intel IP Corporation
- Georg Seidemann
- G02 - OPTICS
Information Patent Grant
Wafer level package structure with internal conductive layer
- Patent number 10,672,731
- Issue date Jun 2, 2020
- Intel IP Corporation
- Sven Albers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic packages with high integration microelectronic dice...
- Patent number 10,622,333
- Issue date Apr 14, 2020
- Intel IP Corporation
- Richard Patten
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic package with illuminated backside exterior
- Patent number 10,411,000
- Issue date Sep 10, 2019
- Intel IP Corporation
- Marc Stephan Dittes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method, apparatus and system to interconnect packaged integrated ci...
- Patent number 10,396,055
- Issue date Aug 27, 2019
- Intel Corporation
- Yong She
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package having wirebonded multi-die stack
- Patent number 10,249,598
- Issue date Apr 2, 2019
- Intel Corporation
- Thorsten Meyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packages including an optical redistribution layer
- Patent number 10,209,466
- Issue date Feb 19, 2019
- Intel IP Corporation
- Georg Seidemann
- G02 - OPTICS
Information Patent Grant
Integrated circuit package having wirebonded multi-die stack
- Patent number 9,972,601
- Issue date May 15, 2018
- Intel Corporation
- Thorsten Meyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic device package
- Patent number 9,859,255
- Issue date Jan 2, 2018
- Intel Corporation
- Jh Yoon
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
PACKAGE STACKING USING CHIP TO WAFER BONDING
- Publication number 20240213225
- Publication date Jun 27, 2024
- Intel Corporation
- Georg SEIDEMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FAN OUT PACKAGING POP MECHANICAL ATTACH METHOD
- Publication number 20230343766
- Publication date Oct 26, 2023
- Intel Corporation
- David O'SULLIVAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK
- Publication number 20230023328
- Publication date Jan 26, 2023
- Intel Corporation
- Thorsten Meyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STACKING USING CHIP TO WAFER BONDING
- Publication number 20220108976
- Publication date Apr 7, 2022
- Intel Corporation
- Georg SEIDEMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC PACKAGES WITH HIGH INTEGRATION MICROELECTRONIC DICE...
- Publication number 20210035950
- Publication date Feb 4, 2021
- Intel IP Corporation
- Richard PATTEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL PACKAGE STRUCTURE WITH INTERNAL CONDUCTIVE LAYER
- Publication number 20200273832
- Publication date Aug 27, 2020
- Intel IP Corporation
- Sven ALBERS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC PACKAGES WITH HIGH INTEGRATION MICROELECTRONIC DICE...
- Publication number 20200219844
- Publication date Jul 9, 2020
- Intel IP Corporation
- Richard PATTEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DIE PACKAGE WITH MORE THAN ONE HANGING DIE
- Publication number 20200176436
- Publication date Jun 4, 2020
- Intel IP Corporation
- Sven ALBERS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NOVEL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP), FLIP-CHIP CHIP SCALE...
- Publication number 20200098698
- Publication date Mar 26, 2020
- Intel Corporation
- Richard PATTEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD, APPARATUS AND SYSTEM TO INTERCONNECT PACKAGED INTEGRATED CI...
- Publication number 20190341372
- Publication date Nov 7, 2019
- Intel Corporation
- Yong SHE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FAN OUT PACKAGING POP MECHANICAL ATTACH METHOD
- Publication number 20190312016
- Publication date Oct 10, 2019
- Intel IP Corporation
- David O'Sullivan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTICAL FIBER CONNECTION ON PACKAGE EDGE
- Publication number 20190121041
- Publication date Apr 25, 2019
- Intel IP Corporation
- Sven Albers
- G02 - OPTICS
Information Patent Application
MICROELECTRONIC PACKAGES WITH HIGH INTEGRATION MICROELECTRONIC DICE...
- Publication number 20190109114
- Publication date Apr 11, 2019
- Intel IP Corporation
- Richard PATTEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGES INCLUDING AN OPTICAL REDISTRIBUTION LAYER
- Publication number 20190072732
- Publication date Mar 7, 2019
- Intel IP Corporation
- Georg Seidemann
- G02 - OPTICS
Information Patent Application
METHOD, APPARATUS AND SYSTEM TO INTERCONNECT PACKAGED INTEGRATED CI...
- Publication number 20190019777
- Publication date Jan 17, 2019
- Intel Corporation
- Yong SHE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL PACKAGE STRUCTURE WITH INTERNAL CONDUCTIVE LAYER
- Publication number 20180358317
- Publication date Dec 13, 2018
- Sven ALBERS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STACKING USING CHIP TO WAFER BONDING
- Publication number 20180331070
- Publication date Nov 15, 2018
- Intel IP Corporation
- Georg SEIDEMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK
- Publication number 20180315737
- Publication date Nov 1, 2018
- Intel Corporation
- Thorsten Meyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK
- Publication number 20180197840
- Publication date Jul 12, 2018
- Intel Corporation
- Thorsten Meyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGES INCLUDING AN OPTICAL REDISTRIBUTION LAYER
- Publication number 20170285280
- Publication date Oct 5, 2017
- Intel IP Corporation
- Georg Seidemann
- G02 - OPTICS
Information Patent Application
Microelectronic Package with Illuminated Backside Exterior
- Publication number 20170284636
- Publication date Oct 5, 2017
- Intel IP Corporation
- Marc Stephan Dittes
- F21 - LIGHTING
Information Patent Application
FLIP-CHIP PACKAGE WITH THERMAL DISSIPATION LAYER
- Publication number 20170178999
- Publication date Jun 22, 2017
- Intel IP Corporation
- Richard Patten
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK
- Publication number 20160276311
- Publication date Sep 22, 2016
- Intel Corporation
- Thorsten Meyer
- H01 - BASIC ELECTRIC ELEMENTS

Richard Patten

Person

Patents Grantslast 30 patents

Package stacking using chip to wafer bonding

Fan out packaging pop mechanical attach method

Microelectronic packages with high integration microelectronic dice...

Wafer level package structure with internal conductive layer

Package stacking using chip to wafer bonding

Method, apparatus and system to interconnect packaged integrated ci...

Microelectronic packages with high integration microelectronic dice...

Semiconductor die package with more than one hanging die

Integrated circuit packages including an optical redistribution layer

Wafer level package structure with internal conductive layer

Microelectronic packages with high integration microelectronic dice...

Microelectronic package with illuminated backside exterior

Method, apparatus and system to interconnect packaged integrated ci...

Integrated circuit package having wirebonded multi-die stack

Integrated circuit packages including an optical redistribution layer

Integrated circuit package having wirebonded multi-die stack

Electronic device package

Patents Applicationslast 30 patents

PACKAGE STACKING USING CHIP TO WAFER BONDING

FAN OUT PACKAGING POP MECHANICAL ATTACH METHOD

INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK

PACKAGE STACKING USING CHIP TO WAFER BONDING

MICROELECTRONIC PACKAGES WITH HIGH INTEGRATION MICROELECTRONIC DICE...

WAFER LEVEL PACKAGE STRUCTURE WITH INTERNAL CONDUCTIVE LAYER

MICROELECTRONIC PACKAGES WITH HIGH INTEGRATION MICROELECTRONIC DICE...

SEMICONDUCTOR DIE PACKAGE WITH MORE THAN ONE HANGING DIE

NOVEL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP), FLIP-CHIP CHIP SCALE...

METHOD, APPARATUS AND SYSTEM TO INTERCONNECT PACKAGED INTEGRATED CI...

FAN OUT PACKAGING POP MECHANICAL ATTACH METHOD

OPTICAL FIBER CONNECTION ON PACKAGE EDGE

MICROELECTRONIC PACKAGES WITH HIGH INTEGRATION MICROELECTRONIC DICE...

INTEGRATED CIRCUIT PACKAGES INCLUDING AN OPTICAL REDISTRIBUTION LAYER

METHOD, APPARATUS AND SYSTEM TO INTERCONNECT PACKAGED INTEGRATED CI...

WAFER LEVEL PACKAGE STRUCTURE WITH INTERNAL CONDUCTIVE LAYER

PACKAGE STACKING USING CHIP TO WAFER BONDING

INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK

INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK

INTEGRATED CIRCUIT PACKAGES INCLUDING AN OPTICAL REDISTRIBUTION LAYER

Microelectronic Package with Illuminated Backside Exterior

FLIP-CHIP PACKAGE WITH THERMAL DISSIPATION LAYER

INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK