Richard Schinella

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for growing thin films
- Patent number 7,081,296
- Issue date Jul 25, 2006
- LSI Logic Corporation
- Sheldon Aronowitz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Process skew results for integrated circuits
- Patent number 7,020,859
- Issue date Mar 28, 2006
- LSI Logic Corporation
- Richard D. Schinella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for planarizing upper surface of damascene wiring structure...
- Patent number 6,881,664
- Issue date Apr 19, 2005
- LSI Logic Corporation
- Wilbur G. Catabay
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Low k dielectric composite layer for integrated circuit structure w...
- Patent number 6,800,940
- Issue date Oct 5, 2004
- LSI Logic Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned alloy capping layers for copper interconnect structures
- Patent number 6,747,358
- Issue date Jun 8, 2004
- LSI Logic Corporation
- Paul Rissman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for growing thin films
- Patent number 6,743,474
- Issue date Jun 1, 2004
- LSI Logic Corporation
- Sheldon Aronowitz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of forming SiGe gate electrode
- Patent number 6,730,588
- Issue date May 4, 2004
- LSI Logic Corporation
- Richard Schinella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reticle formation utilizing metal vaporization
- Patent number 6,673,498
- Issue date Jan 6, 2004
- LSI Logic Corporation
- Sheldon Aronowitz
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method for creating self-aligned alloy capping layers for copper in...
- Patent number 6,566,262
- Issue date May 20, 2003
- LSI Logic Corporation
- Paul Rissman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for application of proximity correction with r...
- Patent number 6,532,585
- Issue date Mar 11, 2003
- LSI Logic Corporation
- Dusan Petranovic
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Substrate processing system
- Patent number 6,518,193
- Issue date Feb 11, 2003
- LSI Logic Corporation
- Kiran Kumar
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Process for forming metal-filled openings in low dielectric constan...
- Patent number 6,503,840
- Issue date Jan 7, 2003
- LSI Logic Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for application of proximity correction with u...
- Patent number 6,499,003
- Issue date Dec 24, 2002
- LSI Logic Corporation
- Edwin Jones
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Interconnection system with lateral barrier layer
- Patent number 6,426,286
- Issue date Jul 30, 2002
- LSI Logic Corporation
- Richard D. Schinella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low k dielectric composite layer for intergrated circuit structure...
- Patent number 6,391,795
- Issue date May 21, 2002
- LSI Logic Corporation
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming trenches and vias in layers of low dielectric c...
- Patent number 6,350,700
- Issue date Feb 26, 2002
- LSI Logic Corporation
- Richard D. Schinella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for general systematic application of proximit...
- Patent number 6,175,953
- Issue date Jan 16, 2001
- LSI Logic Corporation
- Ranko Scepanovic
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method of proximity correction with relative segmentation
- Patent number 6,174,630
- Issue date Jan 16, 2001
- LSI Logic Corporation
- Dusan Petranovic
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Process for making integrated circuit structure comprising local ar...
- Patent number 5,895,261
- Issue date Apr 20, 1999
- LSI Logic Corporation
- Richard Schinella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a barrier metal technology for tungsten plug inter...
- Patent number 5,827,777
- Issue date Oct 27, 1998
- LSI Logic Corporation
- Richard D. Schinella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making self-aligned remote polysilicon contacts
- Patent number 5,674,774
- Issue date Oct 7, 1997
- LSI Logic Corporation
- Nicholas F. Pasch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for making integrated circuit structure comprising local ar...
- Patent number 5,670,425
- Issue date Sep 23, 1997
- LSI Logic Corporation
- Richard Schinella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Optical corrective techniques with reticle formation and reticle st...
- Patent number 5,663,017
- Issue date Sep 2, 1997
- LSI Logic Corporation
- Richard Schinella
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Use of reticle stitching to provide design flexibility
- Patent number 5,652,163
- Issue date Jul 29, 1997
- LSI Logic Corporation
- Richard D. Schinella
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Barrier metal technology for tungsten plug interconnection
- Patent number 5,600,182
- Issue date Feb 4, 1997
- LSI Logic Corporation
- Richard D. Schinella
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Process skew results for integrated circuits
- Publication number 20040241990
- Publication date Dec 2, 2004
- Richard D. Schinella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for growing thin films
- Publication number 20040175947
- Publication date Sep 9, 2004
- LSI Logic Corporation
- Sheldon Aronowitz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Process for planarizing upper surface of damascene wiring structure...
- Publication number 20040009668
- Publication date Jan 15, 2004
- Wilbur G. Catabay
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
Substrate processing system
- Publication number 20030084587
- Publication date May 8, 2003
- LSI Logic Corporation
- Kiran Kumar
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Process for forming metal-filled openings in low dielectric constan...
- Publication number 20020164877
- Publication date Nov 7, 2002
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low k dielectric composite layer for integrated circuit structure w...
- Publication number 20020123243
- Publication date Sep 5, 2002
- Wilbur G. Catabay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Strong phase shift mask substrates
- Publication number 20020064713
- Publication date May 30, 2002
- Richard D. Schinella
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
METHOD AND APPARATUS FOR APPLICATION OF PROXIMITY CORRECTION WITH U...
- Publication number 20020004714
- Publication date Jan 10, 2002
- EDWIN JONES
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Richard Schinella

Person

Patents Grantslast 30 patents

Method for growing thin films

Process skew results for integrated circuits

Process for planarizing upper surface of damascene wiring structure...

Low k dielectric composite layer for integrated circuit structure w...

Self-aligned alloy capping layers for copper interconnect structures

Method for growing thin films

Method of forming SiGe gate electrode

Method for reticle formation utilizing metal vaporization

Method for creating self-aligned alloy capping layers for copper in...

Method and apparatus for application of proximity correction with r...

Substrate processing system

Process for forming metal-filled openings in low dielectric constan...

Method and apparatus for application of proximity correction with u...

Interconnection system with lateral barrier layer

Low k dielectric composite layer for intergrated circuit structure...

Process for forming trenches and vias in layers of low dielectric c...

Method and apparatus for general systematic application of proximit...

Method of proximity correction with relative segmentation

Process for making integrated circuit structure comprising local ar...

Method of making a barrier metal technology for tungsten plug inter...

Method of making self-aligned remote polysilicon contacts

Process for making integrated circuit structure comprising local ar...

Optical corrective techniques with reticle formation and reticle st...

Use of reticle stitching to provide design flexibility

Barrier metal technology for tungsten plug interconnection

Patents Applicationslast 30 patents

Process skew results for integrated circuits

Method for growing thin films

Process for planarizing upper surface of damascene wiring structure...

Substrate processing system

Process for forming metal-filled openings in low dielectric constan...

Low k dielectric composite layer for integrated circuit structure w...

Strong phase shift mask substrates

METHOD AND APPARATUS FOR APPLICATION OF PROXIMITY CORRECTION WITH U...