Eytan Barouch, Uew Hollerbach and Rakesh Vallishayee, “OPTIMASK: An OPC Algorithm for Chrome and Phase-Shift Mask Design,” SPIE vol. 2440, pp. 192-206 (1995). |
Hiroki Futatsuya, Tatsuo Chijimatsu, Satoru Asai, Isamu Hanyu, “Practical Method of Evaluating Two Dimensional Resist Features for Lithographic DRC,” SPIE vol. 3051, pp. 499-508 (1995). |
Richard C. Henderson and Oberdan W. Otto, “CD Data Requirements for Proximity Effect Corrections,” SPIE vol. 2322 Photomask Technology and Management, pp. 218-228 (1994). |
John Stirniman and Michael Rieger, “Optimizing Proximity Correction for Wafer Fabrication Processes,” SPIE vol. 2322 Photomask Technology and Management, pp. 239-246 (1994). |
Robert Socha, Alfred Wong, Myron Cagan, Zoran Krivokapic and Andrew Neureuther, “Effects of Wafer Topography on the Formation of Polysilicon Gates,” SPIE vol. 2440, pp. 361-371. |
Abstract of Japanese Patent Publication No. 06125007, titled “Verifying Method for Layout Data of Semiconductor Device,” published May 6, 1994. |
Abstract of Japanese Patent Publication No. 06083906, titled “Method and Device for Layout Verification,” published Mar. 25, 1994. |
Abstract of Japanese Patent Publication No. 04063460, titled “LSI Layout Pattern Data Checking Apparatus,” published Feb. 28, 1992. |
Abstract of Japanese Patent Publication No. 09288686, titled “Layout Pattern Design Reference/Verification Rule Preparation Supporting Method and System Therefor,” published Nov. 4, 1997. |
Abstract of Japanese Patent Publication No. 09148441, titled “Layout Verification Method and Device,” published Jun. 6, 1997. |
Abstract of Japanese Patent Publication No. 09044535, titled “Layout Editing Method,” published Feb. 14, 1997. |
Abstract of Japanese Patent Publication No. 07021239, titled “Design Rule Check Execution Device,” published Jan. 24, 1995. |
Abstract of Japanese Patent Publication No. 04033168, titled “Layout Pattern Inspection Rule Generation System,” published Feb. 4, 1992. |
Chuang et al.; “Practical applications of 2-D optical proximity corrections for enhanced performance of 0.25 micron random logic devices”; IEEE Electron Dev. Meeting; pp. 483-486; Dec. 1997.* |
Harafuji et al.; “A novel hierarchical approach for proximity effect correction in electron beam lithography”; IEEE Trans. CAD of ICs & Systems; pp. 1508-1514; Oct. 1993. |