Richard T. Schultz

Person

Ft. Collins, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Routing and manufacturing with a minimum area metal structure
- Patent number 11,934,764
- Issue date Mar 19, 2024
- Advanced Micro Devices, Inc.
- Richard Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cross field effect transistor library cell architecture design
- Patent number 11,881,393
- Issue date Jan 23, 2024
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cross field effect transistor (XFET) library architecture power rou...
- Patent number 11,862,640
- Issue date Jan 2, 2024
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cross FET SRAM cell layout
- Patent number 11,778,803
- Issue date Oct 3, 2023
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor chip with stacked conductor lines and air gaps
- Patent number 11,742,289
- Issue date Aug 29, 2023
- Advanced Micro Devices, Inc.
- Richard Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-track bitline scheme for 6T SRAM cells
- Patent number 11,710,698
- Issue date Jul 25, 2023
- Advanced Micro Devices, Inc.
- John J. Wuu
- G11 - INFORMATION STORAGE
Information Patent Grant
Inset power post and strap architecture with reduced voltage droop
- Patent number 11,652,050
- Issue date May 16, 2023
- Advanced Micro Devices, Inc.
- Richard Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Folded cell layout for 6T SRAM cell
- Patent number 11,437,316
- Issue date Sep 6, 2022
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate contact over active region in cell
- Patent number 11,424,336
- Issue date Aug 23, 2022
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power grid architecture and optimization with EUV lithography
- Patent number 11,347,925
- Issue date May 31, 2022
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Standard cell layout architectures and drawing styles for 5nm and b...
- Patent number 11,211,330
- Issue date Dec 28, 2021
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power grid layout designs for integrated circuits
- Patent number 11,189,569
- Issue date Nov 30, 2021
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Metal zero power ground stub route to reduce cell area and improve...
- Patent number 11,120,190
- Issue date Sep 14, 2021
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor chip with stacked conductor lines and air gaps
- Patent number 11,004,791
- Issue date May 11, 2021
- Advanced Micro Devices, Inc.
- Richard Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate contact over active region in cell
- Patent number 10,818,762
- Issue date Oct 27, 2020
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Standard cell and power grid architectures with EUV lithography
- Patent number 10,796,061
- Issue date Oct 6, 2020
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double spacer immersion lithography triple patterning flow and method
- Patent number 10,784,154
- Issue date Sep 22, 2020
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sinusoidal shaped capacitor architecture in oxide
- Patent number 10,756,164
- Issue date Aug 25, 2020
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal zero contact via redundancy on output nodes and inset power r...
- Patent number 10,651,164
- Issue date May 12, 2020
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Oscillating capacitor architecture in polysilicon for improved capa...
- Patent number 10,608,076
- Issue date Mar 31, 2020
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal zero contact via redundancy on output nodes and inset power r...
- Patent number 10,438,937
- Issue date Oct 8, 2019
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double spacer immersion lithography triple patterning flow and method
- Patent number 10,304,728
- Issue date May 28, 2019
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal density distribution for double pattern lithography
- Patent number 10,283,437
- Issue date May 7, 2019
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical gate all around library architecture
- Patent number 10,186,510
- Issue date Jan 22, 2019
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gate all around device architecture with hybrid wafer bond technique
- Patent number 10,068,794
- Issue date Sep 4, 2018
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate all around device architecture with local oxide
- Patent number 9,704,995
- Issue date Jul 11, 2017
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trench silicide and gate open with local interconnect with replacem...
- Patent number 9,006,834
- Issue date Apr 14, 2015
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trench silicide and gate open with local interconnect with replacem...
- Patent number 8,716,124
- Issue date May 6, 2014
- Advanced Micro Devices
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming fins for a FinFET device
- Patent number 8,624,320
- Issue date Jan 7, 2014
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective local interconnect to gate in a self aligned local interc...
- Patent number 8,563,425
- Issue date Oct 22, 2013
- Advanced Micro Devices
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
APPARATUSES AND SYSTEMS FOR OFFSET CROSS FIELD-EFFECT TRANSISTORS
- Publication number 20240145565
- Publication date May 2, 2024
- ADVANCED MICRO DEVICES, INC.
- Richard SCHULTZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE POWER WITH ON-DIE POWER SWITCHES
- Publication number 20240128192
- Publication date Apr 18, 2024
- ADVANCED MICRO DEVICES, INC.
- Suphachai Sutanthavibul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER VIA WITH REDUCED RESISTANCE
- Publication number 20240113022
- Publication date Apr 4, 2024
- ADVANCED MICRO DEVICES, INC.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE POWER DELIVERY AND POWER GRID PATTERN TO SUPPORT 3D DIE ST...
- Publication number 20240105675
- Publication date Mar 28, 2024
- ADVANCED MICRO DEVICES, INC.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOUBLE SIDE TRANSISTORS ON SAME SILICON WAFER
- Publication number 20240038596
- Publication date Feb 1, 2024
- ADVANCED MICRO DEVICES, INC.
- Chandra Sekhar Mandalapu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CROSS FET SRAM CELL LAYOUT
- Publication number 20240032270
- Publication date Jan 25, 2024
- ADVANCED MICRO DEVICES, INC.
- Richard T. Schultz
- G11 - INFORMATION STORAGE
Information Patent Application
CROSS FIELD EFFECT TRANSISTOR (XFET) LIBRARY ARCHITECTURE POWER ROU...
- Publication number 20230096652
- Publication date Mar 30, 2023
- ADVANCED MICRO DEVICES, INC.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CROSS FIELD EFFECT TRANSISTOR (XFET) ARCHITECTURE PROCESS
- Publication number 20230102901
- Publication date Mar 30, 2023
- ADVANCED MICRO DEVICES, INC.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CROSS FET SRAM CELL LAYOUT
- Publication number 20230096892
- Publication date Mar 30, 2023
- ADVANCED MICRO DEVICES, INC.
- Richard T. Schultz
- G11 - INFORMATION STORAGE
Information Patent Application
CROSS FIELD EFFECT TRANSISTOR LIBRARY CELL ARCHITECTURE DESIGN
- Publication number 20230096037
- Publication date Mar 30, 2023
- ADVANCED MICRO DEVICES, INC.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STANDARD CELL DESIGN ARCHITECTURE FOR REDUCED VOLTAGE DROOP UTILIZI...
- Publication number 20230092184
- Publication date Mar 23, 2023
- ADVANCED MICRO DEVICES, INC.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ROUTING AND MANUFACTURING WITH A MINIMUM AREA METAL STRUCTURE
- Publication number 20220414311
- Publication date Dec 29, 2022
- ADVANCED MICRO DEVICES, INC.
- RICHARD SCHULTZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSET POWER POST AND STRAP ARCHITECTURE WITH REDUCED VOLTAGE DROOP
- Publication number 20220208678
- Publication date Jun 30, 2022
- ADVANCED MICRO DEVICES, INC.
- Richard SCHULTZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STANDARD CELL LAYOUT ARCHITECTURES AND DRAWING STYLES FOR 5NM AND B...
- Publication number 20220102275
- Publication date Mar 31, 2022
- ADVANCED MICRO DEVICES, INC.
- Richard T. Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL-TRACK BITLINE SCHEME FOR 6T SRAM CELLS
- Publication number 20220093503
- Publication date Mar 24, 2022
- ADVANCED MICRO DEVICES, INC.
- John J. Wuu
- G11 - INFORMATION STORAGE
Information Patent Application
FOLDED CELL LAYOUT FOR 6T SRAM CELL
- Publication number 20220093504
- Publication date Mar 24, 2022
- ADVANCED MICRO DEVICES, INC.
- Richard T. Schultz
- G11 - INFORMATION STORAGE
Information Patent Application
METAL ZERO POWER GROUND STUB ROUTE TO REDUCE CELL AREA AND IMPROVE...
- Publication number 20210406439
- Publication date Dec 30, 2021
- ADVANCED MICRO DEVICES, INC.
- Richard T. Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR CHIP WITH STACKED CONDUCTOR LINES AND AIR GAPS
- Publication number 20210296233
- Publication date Sep 23, 2021
- ADVANCED MICRO DEVICES, INC.
- Richard SCHULTZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE CONTACT OVER ACTIVE REGION IN CELL
- Publication number 20210028288
- Publication date Jan 28, 2021
- ADVANCED MICRO DEVICES, INC.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SINUSOIDAL SHAPED CAPACITOR ARCHITECTURE IN OXIDE
- Publication number 20200388669
- Publication date Dec 10, 2020
- ADVANCED MICRO DEVICES, INC.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP WITH STACKED CONDUCTOR LINES AND AIR GAPS
- Publication number 20200328155
- Publication date Oct 15, 2020
- ADVANCED MICRO DEVICES, INC.
- Richard SCHULTZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL ZERO CONTACT VIA REDUNDANCY ON OUTPUT NODES AND INSET POWER R...
- Publication number 20200035662
- Publication date Jan 30, 2020
- ADVANCED MICRO DEVICES, INC.
- Richard T. Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GATE CONTACT OVER ACTIVE REGION IN CELL
- Publication number 20190363167
- Publication date Nov 28, 2019
- ADVANCED MICRO DEVICES, INC.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL ZERO CONTACT VIA REDUNDANCY ON OUTPUT NODES AND INSET POWER R...
- Publication number 20190333911
- Publication date Oct 31, 2019
- ADVANCED MICRO DEVICES, INC.
- Richard T. Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOUBLE SPACER IMMERSION LITHOGRAPHY TRIPLE PATTERNING FLOW AND METHOD
- Publication number 20190295885
- Publication date Sep 26, 2019
- ADVANCED MICRO DEVICES, INC.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL ZERO POWER GROUND STUB ROUTE TO REDUCE CELL AREA AND IMPROVE...
- Publication number 20190155979
- Publication date May 23, 2019
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDARD CELL LAYOUT ARCHITECTURES AND DRAWING STYLES FOR 5NM AND B...
- Publication number 20180315709
- Publication date Nov 1, 2018
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOUBLE SPACER IMMERSION LITHOGRAPHY TRIPLE PATTERNING FLOW AND METHOD
- Publication number 20180315645
- Publication date Nov 1, 2018
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER GRID ARCHITECTURE AND OPTIMIZATION WITH EUV LITHOGRAPHY
- Publication number 20180314785
- Publication date Nov 1, 2018
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERTICAL GATE ALL AROUND LIBRARY ARCHITECTURE
- Publication number 20180315751
- Publication date Nov 1, 2018
- Advanced Micro Devices, Inc.
- Richard T. Schultz
- G06 - COMPUTING CALCULATING COUNTING

Richard T. Schultz

Person

Patents Grantslast 30 patents

Routing and manufacturing with a minimum area metal structure

Cross field effect transistor library cell architecture design

Cross field effect transistor (XFET) library architecture power rou...

Cross FET SRAM cell layout

Semiconductor chip with stacked conductor lines and air gaps

Dual-track bitline scheme for 6T SRAM cells

Inset power post and strap architecture with reduced voltage droop

Folded cell layout for 6T SRAM cell

Gate contact over active region in cell

Power grid architecture and optimization with EUV lithography

Standard cell layout architectures and drawing styles for 5nm and b...

Power grid layout designs for integrated circuits

Metal zero power ground stub route to reduce cell area and improve...

Semiconductor chip with stacked conductor lines and air gaps

Gate contact over active region in cell

Standard cell and power grid architectures with EUV lithography

Double spacer immersion lithography triple patterning flow and method

Sinusoidal shaped capacitor architecture in oxide

Metal zero contact via redundancy on output nodes and inset power r...

Oscillating capacitor architecture in polysilicon for improved capa...

Metal zero contact via redundancy on output nodes and inset power r...

Double spacer immersion lithography triple patterning flow and method

Metal density distribution for double pattern lithography

Vertical gate all around library architecture

Gate all around device architecture with hybrid wafer bond technique

Gate all around device architecture with local oxide

Trench silicide and gate open with local interconnect with replacem...

Trench silicide and gate open with local interconnect with replacem...

Process for forming fins for a FinFET device

Selective local interconnect to gate in a self aligned local interc...

Patents Applicationslast 30 patents

APPARATUSES AND SYSTEMS FOR OFFSET CROSS FIELD-EFFECT TRANSISTORS

BACKSIDE POWER WITH ON-DIE POWER SWITCHES

POWER VIA WITH REDUCED RESISTANCE

BACKSIDE POWER DELIVERY AND POWER GRID PATTERN TO SUPPORT 3D DIE ST...

DOUBLE SIDE TRANSISTORS ON SAME SILICON WAFER

CROSS FET SRAM CELL LAYOUT

CROSS FIELD EFFECT TRANSISTOR (XFET) LIBRARY ARCHITECTURE POWER ROU...

CROSS FIELD EFFECT TRANSISTOR (XFET) ARCHITECTURE PROCESS

CROSS FET SRAM CELL LAYOUT

CROSS FIELD EFFECT TRANSISTOR LIBRARY CELL ARCHITECTURE DESIGN

STANDARD CELL DESIGN ARCHITECTURE FOR REDUCED VOLTAGE DROOP UTILIZI...

ROUTING AND MANUFACTURING WITH A MINIMUM AREA METAL STRUCTURE

INSET POWER POST AND STRAP ARCHITECTURE WITH REDUCED VOLTAGE DROOP

STANDARD CELL LAYOUT ARCHITECTURES AND DRAWING STYLES FOR 5NM AND B...

DUAL-TRACK BITLINE SCHEME FOR 6T SRAM CELLS

FOLDED CELL LAYOUT FOR 6T SRAM CELL

METAL ZERO POWER GROUND STUB ROUTE TO REDUCE CELL AREA AND IMPROVE...

SEMICONDUCTOR CHIP WITH STACKED CONDUCTOR LINES AND AIR GAPS

GATE CONTACT OVER ACTIVE REGION IN CELL

SINUSOIDAL SHAPED CAPACITOR ARCHITECTURE IN OXIDE

SEMICONDUCTOR CHIP WITH STACKED CONDUCTOR LINES AND AIR GAPS

METAL ZERO CONTACT VIA REDUNDANCY ON OUTPUT NODES AND INSET POWER R...

GATE CONTACT OVER ACTIVE REGION IN CELL

METAL ZERO CONTACT VIA REDUNDANCY ON OUTPUT NODES AND INSET POWER R...

DOUBLE SPACER IMMERSION LITHOGRAPHY TRIPLE PATTERNING FLOW AND METHOD

METAL ZERO POWER GROUND STUB ROUTE TO REDUCE CELL AREA AND IMPROVE...

STANDARD CELL LAYOUT ARCHITECTURES AND DRAWING STYLES FOR 5NM AND B...

DOUBLE SPACER IMMERSION LITHOGRAPHY TRIPLE PATTERNING FLOW AND METHOD

POWER GRID ARCHITECTURE AND OPTIMIZATION WITH EUV LITHOGRAPHY

VERTICAL GATE ALL AROUND LIBRARY ARCHITECTURE