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Richard Yen-Hsiang Chang
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Palo Alto, CA, US
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Patents Grants
last 30 patents
Information
Patent Grant
Configurable clock network for programmable logic device
Patent number
9,490,812
Issue date
Nov 8, 2016
Altera Corporation
Gregory Starr
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Bit slip circuitry for serial data signals
Patent number
9,054,854
Issue date
Jun 9, 2015
Altera Corporation
Richard Yen-Hsiang Chang
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Bit slip circuitry for serial data signals
Patent number
8,774,305
Issue date
Jul 8, 2014
Altera Corporation
Richard Yen-Hsiang Chang
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Configurable clock network for programmable logic device
Patent number
8,680,913
Issue date
Mar 25, 2014
Altera Corporation
Gregory Starr
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Bit slip circuitry for serial data signals
Patent number
8,477,897
Issue date
Jul 2, 2013
Altera Corporation
Richard Yen-Hsiang Chang
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Configurable clock network for programmable logic device
Patent number
8,441,314
Issue date
May 14, 2013
Altera Corporation
Gregory Starr
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Configurable clock network for programmable logic device
Patent number
8,253,484
Issue date
Aug 28, 2012
Altera Corporation
Gregory Starr
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Configurable clock network for programmable logic device
Patent number
8,072,260
Issue date
Dec 6, 2011
Altera Corporation
Gregory Starr
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Configurable clock network for programmable logic device
Patent number
7,859,329
Issue date
Dec 28, 2010
Altera Corporation
Gregory Starr
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Configurable clock network for programmable logic device
Patent number
7,646,237
Issue date
Jan 12, 2010
Altera Corporation
Gregory Starr
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Configurable clock network for programmable logic device
Patent number
7,286,007
Issue date
Oct 23, 2007
Altera Corporation
Gregory Starr
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Highly configurable PLL architecture for programmable logic
Patent number
7,276,943
Issue date
Oct 2, 2007
Altera Corporation
Gregory W. Starr
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Methods and systems for achieving improved intellectual property pr...
Patent number
7,236,007
Issue date
Jun 26, 2007
Altera Corporation
Richard Y. Chang
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Passage structures for use in low-voltage applications
Patent number
7,119,574
Issue date
Oct 10, 2006
Altera Corporation
Andy L Lee
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Highly configurable PLL architecture for programmable logic
Patent number
7,098,707
Issue date
Aug 29, 2006
Altera Corporation
Gregory W. Starr
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Configurable clock network for programmable logic device
Patent number
7,075,365
Issue date
Jul 11, 2006
Altera Corporation
Gregory Starr
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Techniques for dynamically selecting phases of oscillator signals
Patent number
6,933,761
Issue date
Aug 23, 2005
Altera Corporation
Richard Chang
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Passgate structures for use in low-voltage applications
Patent number
6,661,253
Issue date
Dec 9, 2003
Altera Corporation
Andy L. Lee
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Differential interconnection circuits in programmable logic devices
Patent number
6,515,508
Issue date
Feb 4, 2003
Altera Corporation
Wanli Chang
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Memory controller for decoding a compressed/encoded video data frame
Patent number
5,923,665
Issue date
Jul 13, 1999
Cirrus Logic, Inc.
Yuanyuan Sun
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Memory controller for decoding a compressed/encoded video data frame
Patent number
5,838,380
Issue date
Nov 17, 1998
Cirrus Logic, Inc.
Yuanyuan Sun
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Stream synchronization method and apparatus for MPEG playback system
Patent number
5,815,634
Issue date
Sep 29, 1998
Cirrus Logic, Inc.
Daniel T. Daum
G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information
Patent Grant
Programmable audio-video synchronization method and apparatus for m...
Patent number
5,594,660
Issue date
Jan 14, 1997
Cirrus Logic, Inc.
Chih-Ta Sung
G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Patents Applications
last 30 patents
Information
Patent Application
Passgate structures for use in low-voltage applications
Publication number
20070008000
Publication date
Jan 11, 2007
Andy L. Lee
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Application
Highly configurable PLL architecture for programmable logic
Publication number
20060250168
Publication date
Nov 9, 2006
Gregory W. Starr
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Application
Dynamic phase alignment methods and apparatus
Publication number
20050259775
Publication date
Nov 24, 2005
Altera Corporation
Richard Yen-Hsiang Chang
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Application
Highly configurable PLL architecture for programmable logic
Publication number
20050200390
Publication date
Sep 15, 2005
Altera Corporation
Gregory W. Starr
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Application
Techniques for dynamically selecting phases of oscillator signals
Publication number
20040257137
Publication date
Dec 23, 2004
Altera Corporation
Richard Chang
H03 - BASIC ELECTRONIC CIRCUITRY