Robert D. Shur

Person

Los Altos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and system for simulation of mixed-language circuit designs
- Patent number 7,424,703
- Issue date Sep 9, 2008
- Cadence Design Systems, Inc.
- Edwin A. Harcourt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated optimization of hierarchical netlists
- Patent number 5,956,257
- Issue date Sep 21, 1999
- VLSI Technology, Inc.
- Arnold Ginetti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced dynamic programming method for technology mapping of combi...
- Patent number 5,787,010
- Issue date Jul 28, 1998
- Thomas J. Schaefer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector-specific testability circuitry
- Patent number 5,483,544
- Issue date Jan 9, 1996
- VLSI Technology, Inc.
- Robert D. Shur
- G11 - INFORMATION STORAGE
Information Patent Grant
Buffer circuit design using back track searching of site trees
- Patent number 5,402,356
- Issue date Mar 28, 1995
- VLSI Technology, Inc.
- Thomas J. Schaefer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for synthesizing logic circuits with timing const...
- Patent number 5,402,357
- Issue date Mar 28, 1995
- VLSI Technology, Inc.
- Thomas J. Schaefer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for predicting capacitance of connection nets on an integrat...
- Patent number 5,295,088
- Issue date Mar 15, 1994
- VLSI Technology, Inc.
- Mark R. Hartoog
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit simulation system with wake-up latency
- Patent number 5,272,651
- Issue date Dec 21, 1993
- VLSI Technology, Inc.
- Steve Bush
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for setting capacitive constraints on synthesized...
- Patent number 5,197,015
- Issue date Mar 23, 1993
- VLSI Technology, Inc.
- Mark R. Hartoog
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated parity-based testing for integrated circuits
- Patent number 5,193,092
- Issue date Mar 9, 1993
- VLSI Technology, Inc.
- Mark R. Hartoog
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Event-controlled LCC stimulation
- Patent number 5,068,812
- Issue date Nov 26, 1991
- VLSI Technology, Inc.
- Thomas J. Schaefer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Levelized logic simulator with fenced evaluation
- Patent number 5,062,067
- Issue date Oct 29, 1991
- VLSI Technology, Inc.
- Thomas J. Schaefer
- G06 - COMPUTING CALCULATING COUNTING

Robert D. Shur

Person

Patents Grantslast 30 patents

Method and system for simulation of mixed-language circuit designs

Automated optimization of hierarchical netlists

Enhanced dynamic programming method for technology mapping of combi...

Vector-specific testability circuitry

Buffer circuit design using back track searching of site trees

System and method for synthesizing logic circuits with timing const...

Method for predicting capacitance of connection nets on an integrat...

Circuit simulation system with wake-up latency

System and method for setting capacitive constraints on synthesized...

Integrated parity-based testing for integrated circuits

Event-controlled LCC stimulation

Levelized logic simulator with fenced evaluation