Robert E. Busch

Person

Essex Junction, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Design structure for content addressable memory
- Patent number 7,464,217
- Issue date Dec 9, 2008
- International Business Machines Corporation
- Geordie M. Braceras
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory structure
- Patent number 7,337,268
- Issue date Feb 26, 2008
- International Business Machines Corporation
- George M. Braceras
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory structure
- Patent number 7,120,732
- Issue date Oct 10, 2006
- International Business Machines Corporation
- George M. Braceras
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with data line steering and bitline redundancy
- Patent number 7,117,400
- Issue date Oct 3, 2006
- International Business Machines Corporation
- Kevin A. Batson
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit having register configuration sets
- Patent number 6,941,435
- Issue date Sep 6, 2005
- International Business Machines Corporation
- Anthony R. Bonaccio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundant array architecture for word replacement in CAM
- Patent number 6,791,855
- Issue date Sep 14, 2004
- International Business Machines Corporation
- Kevin A. Batson
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for combining refresh operation with parity validation in a...
- Patent number 6,760,881
- Issue date Jul 6, 2004
- International Business Machines Corporation
- Kevin A. Batson
- G11 - INFORMATION STORAGE
Information Patent Grant
CAM cell with interdigitated search and bit lines
- Patent number 6,760,240
- Issue date Jul 6, 2004
- International Business Machines Corporation
- Robert E. Busch
- G11 - INFORMATION STORAGE
Information Patent Grant
Redundant array architecture for word replacement in CAM
- Patent number 6,728,123
- Issue date Apr 27, 2004
- International Business Machines Corporation
- Kevin A. Batson
- G11 - INFORMATION STORAGE
Information Patent Grant
High reliability content-addressable memory using shadow content-ad...
- Patent number 6,687,144
- Issue date Feb 3, 2004
- International Business Machines Corporation
- Kevin A. Batson
- G11 - INFORMATION STORAGE
Information Patent Grant
High reliability content-addressable memory using shadow content-ad...
- Patent number 6,650,561
- Issue date Nov 18, 2003
- International Business Machines Corporation
- Kevin A. Batson
- G11 - INFORMATION STORAGE
Information Patent Grant
Alternating reference wordline scheme for fast DRAM
- Patent number 6,501,675
- Issue date Dec 31, 2002
- International Business Machines Corporation
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Use of search lines as global bitlines in a cam design
- Patent number 6,487,101
- Issue date Nov 26, 2002
- International Business Machines Corporation
- Jonathan B. Ashbrook
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for conserving power in a content addressable mem...
- Patent number 6,442,055
- Issue date Aug 27, 2002
- International Business Machines Corporation
- Robert E. Busch
- G11 - INFORMATION STORAGE
Information Patent Grant
Dram CAM cell with hidden refresh
- Patent number 6,430,073
- Issue date Aug 6, 2002
- International Business Machines Corporation
- Kevin A. Batson
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device having resistive bitline contact testing
- Patent number 6,208,572
- Issue date Mar 27, 2001
- International Business Machines Corporation
- R. Dean Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Scannable fuse latches
- Patent number 6,201,750
- Issue date Mar 13, 2001
- International Business Machines Corporation
- Robert E. Busch
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock synchronization scheme for fractional multiplication systems
- Patent number 5,691,660
- Issue date Nov 25, 1997
- International Business Machines Corporation
- Robert Edward Busch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic bus with singular central precharge
- Patent number 5,633,605
- Issue date May 27, 1997
- International Business Machines Corporation
- Jeffrey S. Zimmerman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for multiple memory bank selection
- Patent number 5,530,836
- Issue date Jun 25, 1996
- International Business Machines Corporation
- Robert E. Busch
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast access memory structure
- Patent number 5,276,846
- Issue date Jan 4, 1994
- International Business Machines Corporation
- Frederick J. Aichelmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple mode-set for IC chip
- Patent number 5,036,495
- Issue date Jul 30, 1991
- International Business Machines Corp.
- Robert E. Busch
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory module utilizing partially defective memory chips
- Patent number 4,992,984
- Issue date Feb 12, 1991
- International Business Machines Corporation
- Robert E. Busch
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for providing a dual sense amplifier with divi...
- Patent number 4,807,195
- Issue date Feb 21, 1989
- International Business Machines Corporation
- Robert E. Busch
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DESIGN STRUCTURE FOR CONTENT ADDRESSABLE MEMORY
- Publication number 20080055956
- Publication date Mar 6, 2008
- Geordie M. Braceras
- G11 - INFORMATION STORAGE
Information Patent Application
CONTENT ADDRESSABLE MEMORY STRUCTURE
- Publication number 20070014138
- Publication date Jan 18, 2007
- International Business Machines Corporation
- George M. Braceras
- G11 - INFORMATION STORAGE
Information Patent Application
CONTENT ADDRESSABLE MEMORY STRUCTURE
- Publication number 20050185436
- Publication date Aug 25, 2005
- International Business Machines Corporation
- George M. Braceras
- G11 - INFORMATION STORAGE
Information Patent Application
Memory device with data line steering and bitline redundancy
- Publication number 20040153899
- Publication date Aug 5, 2004
- International Business Machines Corporation
- Kevin A. Batson
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT HAVING REGISTER CONFIGURATION SETS
- Publication number 20040143715
- Publication date Jul 22, 2004
- International Business Machines Corporation
- Anthony R. Bonaccio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CAM CELL WITH INTERDIGITATED SEARCH AND BIT LINES
- Publication number 20040100830
- Publication date May 27, 2004
- International Business Machines Corporation
- Robert E. Busch
- G11 - INFORMATION STORAGE
Information Patent Application
Redundant array architecture for word replacement in CAM
- Publication number 20040052134
- Publication date Mar 18, 2004
- Kevin A. Batson
- G11 - INFORMATION STORAGE
Information Patent Application
High reliability content-addressable memory using shadow content-ad...
- Publication number 20030202371
- Publication date Oct 30, 2003
- Kevin A. Batson
- G11 - INFORMATION STORAGE
Information Patent Application
REDUNDANT ARRAY ARCHITECTURE FOR WORD REPLACEMENT IN CAM
- Publication number 20030193822
- Publication date Oct 16, 2003
- International Business Machines Corporation
- Kevin A. Batson
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH RELIABILITY CONTENT-ADDRESSABLE MEMORY USING SHADOW CONTENT-AD...
- Publication number 20030142525
- Publication date Jul 31, 2003
- International Business Machines Corporation
- Kevin A. Batson
- G11 - INFORMATION STORAGE
Information Patent Application
Method for combining refresh operation with parity validation in a...
- Publication number 20030074630
- Publication date Apr 17, 2003
- Kevin A. Batson
- G11 - INFORMATION STORAGE
Information Patent Application
ALTERNATING REFERENCE WORDLINE SCHEME FOR FAST DRAM
- Publication number 20020176275
- Publication date Nov 28, 2002
- International Business Machines Corporation
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM CAM CELL WITH HIDDEN REFRESH
- Publication number 20020067632
- Publication date Jun 6, 2002
- Kevin A. Batson
- G11 - INFORMATION STORAGE

Robert E. Busch

Person

Patents Grantslast 30 patents

Design structure for content addressable memory

Content addressable memory structure

Content addressable memory structure

Memory device with data line steering and bitline redundancy

Integrated circuit having register configuration sets

Redundant array architecture for word replacement in CAM

Method for combining refresh operation with parity validation in a...

CAM cell with interdigitated search and bit lines

Redundant array architecture for word replacement in CAM

High reliability content-addressable memory using shadow content-ad...

High reliability content-addressable memory using shadow content-ad...

Alternating reference wordline scheme for fast DRAM

Use of search lines as global bitlines in a cam design

System and method for conserving power in a content addressable mem...

Dram CAM cell with hidden refresh

Semiconductor memory device having resistive bitline contact testing

Scannable fuse latches

Clock synchronization scheme for fractional multiplication systems

Dynamic bus with singular central precharge

Method and apparatus for multiple memory bank selection

Fast access memory structure

Multiple mode-set for IC chip

Memory module utilizing partially defective memory chips

Apparatus and method for providing a dual sense amplifier with divi...

Patents Applicationslast 30 patents

DESIGN STRUCTURE FOR CONTENT ADDRESSABLE MEMORY

CONTENT ADDRESSABLE MEMORY STRUCTURE

CONTENT ADDRESSABLE MEMORY STRUCTURE

Memory device with data line steering and bitline redundancy

INTEGRATED CIRCUIT HAVING REGISTER CONFIGURATION SETS

CAM CELL WITH INTERDIGITATED SEARCH AND BIT LINES

Redundant array architecture for word replacement in CAM

High reliability content-addressable memory using shadow content-ad...

REDUNDANT ARRAY ARCHITECTURE FOR WORD REPLACEMENT IN CAM

HIGH RELIABILITY CONTENT-ADDRESSABLE MEMORY USING SHADOW CONTENT-AD...

Method for combining refresh operation with parity validation in a...

ALTERNATING REFERENCE WORDLINE SCHEME FOR FAST DRAM

DRAM CAM CELL WITH HIDDEN REFRESH