Robert E. Strout II

Person

Livermore, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for user side scheduling in a multiprocessor o...
- Patent number 6,195,676
- Issue date Feb 27, 2001
- Silicon Graphics, Inc.
- George A. Spix
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for accessing global registers in a multiproce...
- Patent number 5,524,255
- Issue date Jun 4, 1996
- Cray Research, Inc.
- Douglas R. Beard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual level scheduling of processes to multiple parallel regions of...
- Patent number 5,339,415
- Issue date Aug 16, 1994
- Cray Research, Inc.
- Robert E. Strout
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast interrupt mechanism for interrupting processors in parallel in...
- Patent number 5,193,187
- Issue date Mar 9, 1993
- SuperComputer Systems Limited Partnership
- Robert E. Strout
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for controlling a highly parallel multiprocessor...
- Patent number 5,179,702
- Issue date Jan 12, 1993
- SuperComputer Systems Limited Partnership
- George A. Spix
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer with integrated hierarchical representation (IHR) of progr...
- Patent number 5,175,856
- Issue date Dec 29, 1992
- SuperComputer Systems Limited Partnership
- Don A. Van Dyke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global registers for a multiprocessor system
- Patent number 5,165,038
- Issue date Nov 17, 1992
- SuperComputer Systems Limited Partnership
- Douglas R. Beard
- G06 - COMPUTING CALCULATING COUNTING

Robert E. Strout II

Person

Patents Grantslast 30 patents

Method and apparatus for user side scheduling in a multiprocessor o...

Method and apparatus for accessing global registers in a multiproce...

Dual level scheduling of processes to multiple parallel regions of...

Fast interrupt mechanism for interrupting processors in parallel in...

System and method for controlling a highly parallel multiprocessor...

Computer with integrated hierarchical representation (IHR) of progr...

Global registers for a multiprocessor system