Robert J. Munoz

Person

Round Rock, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus to execute a workload in an edge environment
- Patent number 11,711,268
- Issue date Jul 25, 2023
- Intel Corporation
- Ned Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Removable interposer
- Patent number 11,251,171
- Issue date Feb 15, 2022
- Intel Corporation
- Michael Rifani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shaping of post-scheduling network pipeline jitter
- Patent number 10,812,402
- Issue date Oct 20, 2020
- Intel Corporation
- Robert Southworth
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for packet transmit scheduling
- Patent number 10,791,057
- Issue date Sep 29, 2020
- Intel Corporation
- Sarig Livne
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hierarchical self-organizing classification processing in a network...
- Patent number 9,755,947
- Issue date Sep 5, 2017
- Intel Corporation
- Robert J. Munoz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Address learning and aging for network bridging in a network processor
- Patent number 9,727,508
- Issue date Aug 8, 2017
- Intel Corporation
- Robert J. Munoz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Network switch with external buffering via looparound path
- Patent number 9,485,200
- Issue date Nov 1, 2016
- Intel Corporation
- Robert J. Munoz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Packet data processor in a communications processor architecture
- Patent number 9,444,737
- Issue date Sep 13, 2016
- Intel Corporation
- Robert J. Munoz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for providing cache-aware lightweight producer co...
- Patent number 9,304,920
- Issue date Apr 5, 2016
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Robert J. Munoz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network communications processor architecture
- Patent number 9,081,742
- Issue date Jul 14, 2015
- Intel Corporation
- David P. Sonnier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Packet reassembly processing
- Patent number 9,065,761
- Issue date Jun 23, 2015
- Intel Corporation
- Robert J. Munoz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Sharing of internal pipeline resources of a network processor with...
- Patent number 8,949,578
- Issue date Feb 3, 2015
- LSI Corporation
- Joseph A. Manzella
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Packet assembly module for multi-core, multi-thread network processors
- Patent number 8,761,204
- Issue date Jun 24, 2014
- LSI Corporation
- James T. Clee
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuitry for determining network operations in a network device by...
- Patent number 8,031,706
- Issue date Oct 4, 2011
- Agere Systems Inc.
- Vinoj N. Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods and apparatus for performing network operations on packets...
- Patent number 7,817,629
- Issue date Oct 19, 2010
- Agere Systems Inc.
- Robert J. Munoz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
PACKAGING ARCHITECTURE FOR MODULAR DIE INTEROPERABILITY
- Publication number 20230197677
- Publication date Jun 22, 2023
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGING ARCHITECTURE WITH PATTERNED THROUGH-DIELECTRIC VIAS AND R...
- Publication number 20230187362
- Publication date Jun 15, 2023
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINE-GRAINED DISAGGREGATED SERVER ARCHITECTURE
- Publication number 20230187407
- Publication date Jun 15, 2023
- Intel Corporation
- Carleton L. Molnar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED PACKAGING ARCHITECTURE WITH SOLDER AND NON-SOLDER INTERC...
- Publication number 20230170327
- Publication date Jun 1, 2023
- Intel Corporation
- Jin Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TEST AND DEBUG SUPPORT WITH HBI CHIPLET ARCHITECTURE
- Publication number 20230095914
- Publication date Mar 30, 2023
- Intel Corporation
- Gerald PASDAST
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND APPARATUS TO EXECUTE A WORKLOAD IN AN EDGE ENVIRONMENT
- Publication number 20200167196
- Publication date May 28, 2020
- Intel Corporation
- Ned Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REMOVABLE INTERPOSER
- Publication number 20190385994
- Publication date Dec 19, 2019
- Intel Corporation
- Michael Rifani
- G02 - OPTICS
Information Patent Application
SHAPING OF POST-SCHEDULING NETWORK PIPELINE JITTER
- Publication number 20190140964
- Publication date May 9, 2019
- Robert Southworth
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNIQUES FOR PACKET TRANSMIT SCHEDULING
- Publication number 20190068507
- Publication date Feb 28, 2019
- Intel Corporation
- Sarig LIVNE
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM AND METHOD FOR PROVIDING CACHE-AWARE LIGHTWEIGHT PRODUCER CO...
- Publication number 20140351519
- Publication date Nov 27, 2014
- Robert J. Munoz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR LARGE OBJECT CACHE MANAGEMENT IN A NETWORK
- Publication number 20140258375
- Publication date Sep 11, 2014
- LSI Corporation
- Robert J. Munoz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PACKET DATA PROCESSOR IN A COMMUNICATIONS PROCESSOR ARCHITECTURE
- Publication number 20140153575
- Publication date Jun 5, 2014
- LSI Corporation
- Robert J. Munoz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Hierarchical Self-Organizing Classification Processing in a Network...
- Publication number 20130142205
- Publication date Jun 6, 2013
- LSI Corporation
- Robert J. Munoz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK SWITCH WITH EXTERNAL BUFFERING VIA LOOPAROUND PATH
- Publication number 20130128896
- Publication date May 23, 2013
- LSI Corporation
- Robert J. Munoz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ADDRESS LEARNING AND AGING FOR NETWORK BRIDGING IN A NETWORK PROCESSOR
- Publication number 20130097345
- Publication date Apr 18, 2013
- LSI Corporation
- Robert J. Munoz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKET REASSEMBLY PROCESSING
- Publication number 20130028264
- Publication date Jan 31, 2013
- LSI CORPORATION
- Robert J. Munoz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SHARING OF INTERNAL PIPELINE RESOURCES OF A NETWORK PROCESSOR WITH...
- Publication number 20120300772
- Publication date Nov 29, 2012
- LSI CORPORATION
- Joseph A. Manzella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKET ASSEMBLY MODULE FOR MULTI-CORE, MULTI-THREAD NETWORK PROCESSORS
- Publication number 20120155495
- Publication date Jun 21, 2012
- James T. Clee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Network Communications Processor Architecture
- Publication number 20100293312
- Publication date Nov 18, 2010
- David P. Sonnier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatus for Performing Packet Processing Operations i...
- Publication number 20080080505
- Publication date Apr 3, 2008
- Robert J. Munoz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Methods and Apparatus for Performing Network Operations in Network...
- Publication number 20070263619
- Publication date Nov 15, 2007
- Robert J. Munoz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Circuitry for determining network operations in a network device
- Publication number 20070115984
- Publication date May 24, 2007
- Vinoj N. Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Robert J. Munoz

Person

Patents Grantslast 30 patents

Methods and apparatus to execute a workload in an edge environment

Removable interposer

Shaping of post-scheduling network pipeline jitter

Techniques for packet transmit scheduling

Hierarchical self-organizing classification processing in a network...

Address learning and aging for network bridging in a network processor

Network switch with external buffering via looparound path

Packet data processor in a communications processor architecture

System and method for providing cache-aware lightweight producer co...

Network communications processor architecture

Packet reassembly processing

Sharing of internal pipeline resources of a network processor with...

Packet assembly module for multi-core, multi-thread network processors

Circuitry for determining network operations in a network device by...

Methods and apparatus for performing network operations on packets...

Patents Applicationslast 30 patents

PACKAGING ARCHITECTURE FOR MODULAR DIE INTEROPERABILITY

PACKAGING ARCHITECTURE WITH PATTERNED THROUGH-DIELECTRIC VIAS AND R...

FINE-GRAINED DISAGGREGATED SERVER ARCHITECTURE

INTEGRATED PACKAGING ARCHITECTURE WITH SOLDER AND NON-SOLDER INTERC...

TEST AND DEBUG SUPPORT WITH HBI CHIPLET ARCHITECTURE

METHODS AND APPARATUS TO EXECUTE A WORKLOAD IN AN EDGE ENVIRONMENT

REMOVABLE INTERPOSER

SHAPING OF POST-SCHEDULING NETWORK PIPELINE JITTER

TECHNIQUES FOR PACKET TRANSMIT SCHEDULING

SYSTEM AND METHOD FOR PROVIDING CACHE-AWARE LIGHTWEIGHT PRODUCER CO...

SYSTEM AND METHOD FOR LARGE OBJECT CACHE MANAGEMENT IN A NETWORK

PACKET DATA PROCESSOR IN A COMMUNICATIONS PROCESSOR ARCHITECTURE

Hierarchical Self-Organizing Classification Processing in a Network...

NETWORK SWITCH WITH EXTERNAL BUFFERING VIA LOOPAROUND PATH

ADDRESS LEARNING AND AGING FOR NETWORK BRIDGING IN A NETWORK PROCESSOR

PACKET REASSEMBLY PROCESSING

SHARING OF INTERNAL PIPELINE RESOURCES OF A NETWORK PROCESSOR WITH...

PACKET ASSEMBLY MODULE FOR MULTI-CORE, MULTI-THREAD NETWORK PROCESSORS

Network Communications Processor Architecture

Methods and Apparatus for Performing Packet Processing Operations i...

Methods and Apparatus for Performing Network Operations in Network...

Circuitry for determining network operations in a network device