Robert J. Safranek

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
High performance interconnect
- Patent number 12,197,357
- Issue date Jan 14, 2025
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 12,189,550
- Issue date Jan 7, 2025
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Devices transferring cache lines, including metadata on external links
- Patent number 11,880,686
- Issue date Jan 23, 2024
- Ampere Computing LLC
- Robert James Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for sequencing data checks in a packet
- Patent number 11,868,209
- Issue date Jan 9, 2024
- Ampere Computing LLC
- Matthew Robert Erler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 11,741,030
- Issue date Aug 29, 2023
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for sequencing data checks in a packet
- Patent number 11,481,270
- Issue date Oct 25, 2022
- Ampere Computing LLC
- Matthew Robert Erler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 11,269,793
- Issue date Mar 8, 2022
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple transaction data flow control unit for high-speed intercon...
- Patent number 11,061,850
- Issue date Jul 13, 2021
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multichip package link
- Patent number 11,003,610
- Issue date May 11, 2021
- Intel Corporation
- Zuoguo Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multichip package link
- Patent number 10,552,357
- Issue date Feb 4, 2020
- Intel Corporation
- Zuoguo J. Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple transaction data flow control unit for high-speed intercon...
- Patent number 10,503,688
- Issue date Dec 10, 2019
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect link layer
- Patent number 10,365,965
- Issue date Jul 30, 2019
- Intel Corporation
- Jeff Willey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect link layer
- Patent number 10,360,098
- Issue date Jul 23, 2019
- Intel Corporation
- Jeff Willey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect coherence protocol resolving conflict...
- Patent number 10,268,583
- Issue date Apr 23, 2019
- Intel Corporation
- Robert Beers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 10,248,591
- Issue date Apr 2, 2019
- Intel Corporation
- Robert J. Safranek
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multislot link layer flit wherein flit includes three or more slots...
- Patent number 10,204,064
- Issue date Feb 12, 2019
- Intel Corporation
- Jeff Willey
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multiple transaction data flow control unit for high-speed intercon...
- Patent number 10,078,617
- Issue date Sep 18, 2018
- Intel Corporation
- Robert J. Safranek
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multichip package link
- Patent number 10,073,808
- Issue date Sep 11, 2018
- Intel Corporation
- Zuoguo J. Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Satisfying memory ordering requirements between partial reads and n...
- Patent number 10,019,366
- Issue date Jul 10, 2018
- Intel Corporation
- Robert H. Beers
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for entering a low-power link state
- Patent number 9,813,998
- Issue date Nov 7, 2017
- Intel Corporation
- Shaun M. Conrad
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Cross-die interface snoop or global observation message ordering
- Patent number 9,785,556
- Issue date Oct 10, 2017
- Intel Corporation
- Ramacharan Sundararaman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multislot link layer flit wherein flit includes three or more slots...
- Patent number 9,753,885
- Issue date Sep 5, 2017
- Intel Corporation
- Jeff Willey
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Satisfying memory ordering requirements between partial reads and n...
- Patent number 9,703,712
- Issue date Jul 11, 2017
- Intel Corporation
- Robert H. Beers
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High performance interconnect
- Patent number 9,626,321
- Issue date Apr 18, 2017
- Intel Corporation
- Robert J. Safranek
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High performance interconnect link layer
- Patent number 9,479,196
- Issue date Oct 25, 2016
- Intel Corporation
- Jeff Willey
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple transaction data flow control unit for high-speed intercon...
- Patent number 9,442,879
- Issue date Sep 13, 2016
- Intel Corporation
- Robert J. Safranek
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High performance interconnect link layer
- Patent number 9,444,492
- Issue date Sep 13, 2016
- Intel Corporation
- Jeff Willey
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Raw memory transaction support
- Patent number 9,208,110
- Issue date Dec 8, 2015
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing packet size in a communication protocol
- Patent number 9,148,485
- Issue date Sep 29, 2015
- Intel Corporation
- Phanindra K. Mannava
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Satisfying memory ordering requirements between partial reads and n...
- Patent number 9,058,271
- Issue date Jun 16, 2015
- Intel Corporation
- Robert H. Beers
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
DEVICES TRANSFERRING CACHE LINES, INCLUDING METADATA ON EXTERNAL LINKS
- Publication number 20240134650
- Publication date Apr 25, 2024
- Ampere Computing LLC
- Robert James Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20240012772
- Publication date Jan 11, 2024
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICES TRANSFERRING CACHE LINES, INCLUDING METADATA ON EXTERNAL LINKS
- Publication number 20230409332
- Publication date Dec 21, 2023
- Ampere Computing LLC
- Robert James Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR SEQUENCING DATA CHECKS IN A PACKET
- Publication number 20230058854
- Publication date Feb 23, 2023
- Ampere Computing LLC
- Matthew Robert ERLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES, SYSTEMS, AND METHODS FOR IMPLIED SEQUENCE NUMBERING OF...
- Publication number 20220407813
- Publication date Dec 22, 2022
- Ampere Computing LLC
- Matthew Robert Erler
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND SYSTEM FOR DATA TRANSACTIONS ON A COMMUNICATIONS INTERFACE
- Publication number 20220405223
- Publication date Dec 22, 2022
- Ampere Computing LLC
- Matthew Robert ERLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20220114122
- Publication date Apr 14, 2022
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20210117350
- Publication date Apr 22, 2021
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20200356502
- Publication date Nov 12, 2020
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICHIP PACKAGE LINK
- Publication number 20200320031
- Publication date Oct 8, 2020
- Intel Corporation
- Zuoguo Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE TRANSACTION DATA FLOW CONTROL UNIT FOR HIGH-SPEED INTERCON...
- Publication number 20200110726
- Publication date Apr 9, 2020
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20190391939
- Publication date Dec 26, 2019
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE TRANSACTION DATA FLOW CONTROL UNIT FOR HIGH-SPEED INTERCON...
- Publication number 20190188178
- Publication date Jun 20, 2019
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING MULTI-SOCKET MEMORY COHERENCY USING CROSS-SOCKET SNOOP FI...
- Publication number 20190012265
- Publication date Jan 10, 2019
- QUALCOMM Incorporated
- Robert James Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICHIP PACKAGE LINK
- Publication number 20180300275
- Publication date Oct 18, 2018
- Intel Corporation
- Zuoguo J. Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTISLOT LINK LAYER FLIT WHEREIN FLIT INCLUDES THREE OR MORE SLOTS...
- Publication number 20180143937
- Publication date May 24, 2018
- Intel Corporation
- Jeff Willey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT LINK LAYER
- Publication number 20180011759
- Publication date Jan 11, 2018
- Intel Corporation
- Jeff Willey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...
- Publication number 20170308471
- Publication date Oct 26, 2017
- Intel Corporation
- Robert H. Beers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT LINK LAYER
- Publication number 20170123894
- Publication date May 4, 2017
- Intel Corporation
- Jeff Willey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20170109315
- Publication date Apr 20, 2017
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICHIP PACKAGE LINK
- Publication number 20170083475
- Publication date Mar 23, 2017
- Intel Corporation
- Zuoguo J. Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE TRANSACTION DATA FLOW CONTROL UNIT FOR HIGH-SPEED INTERCON...
- Publication number 20160378710
- Publication date Dec 29, 2016
- lntel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSS-DIE INTERFACE SNOOP OR GLOBAL OBSERVATION MESSAGE ORDERING
- Publication number 20160179673
- Publication date Jun 23, 2016
- Intel Corporation
- RAMACHARAN SUNDARARAMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTISLOT LINK LAYER FLIT
- Publication number 20150261711
- Publication date Sep 17, 2015
- Jeff Willey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT LINK LAYER
- Publication number 20150180507
- Publication date Jun 25, 2015
- Intel Corporation
- Jeff Willey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...
- Publication number 20150178210
- Publication date Jun 25, 2015
- Intel Corporation
- Robert H. Beers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL
- Publication number 20150089161
- Publication date Mar 26, 2015
- Robert Beers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE TRANSACTION DATA FLOW CONTROL UNIT FOR HIGH-SPEED INTERCON...
- Publication number 20140372658
- Publication date Dec 18, 2014
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL
- Publication number 20140115268
- Publication date Apr 24, 2014
- Robert Beers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...
- Publication number 20140115275
- Publication date Apr 24, 2014
- Robert H. Beers
- G06 - COMPUTING CALCULATING COUNTING

Robert J. Safranek

Person

Patents Grantslast 30 patents

High performance interconnect

High performance interconnect

Devices transferring cache lines, including metadata on external links

Method and system for sequencing data checks in a packet

High performance interconnect

Method and system for sequencing data checks in a packet

High performance interconnect

Multiple transaction data flow control unit for high-speed intercon...

Multichip package link

Multichip package link

Multiple transaction data flow control unit for high-speed intercon...

High performance interconnect link layer

High performance interconnect link layer

High performance interconnect coherence protocol resolving conflict...

High performance interconnect

Multislot link layer flit wherein flit includes three or more slots...

Multiple transaction data flow control unit for high-speed intercon...

Multichip package link

Satisfying memory ordering requirements between partial reads and n...

Techniques for entering a low-power link state

Cross-die interface snoop or global observation message ordering

Multislot link layer flit wherein flit includes three or more slots...

Satisfying memory ordering requirements between partial reads and n...

High performance interconnect

High performance interconnect link layer

Multiple transaction data flow control unit for high-speed intercon...

High performance interconnect link layer

Raw memory transaction support

Reducing packet size in a communication protocol

Satisfying memory ordering requirements between partial reads and n...

Patents Applicationslast 30 patents

DEVICES TRANSFERRING CACHE LINES, INCLUDING METADATA ON EXTERNAL LINKS

HIGH PERFORMANCE INTERCONNECT

DEVICES TRANSFERRING CACHE LINES, INCLUDING METADATA ON EXTERNAL LINKS

METHOD AND SYSTEM FOR SEQUENCING DATA CHECKS IN A PACKET

APPARATUSES, SYSTEMS, AND METHODS FOR IMPLIED SEQUENCE NUMBERING OF...

METHOD AND SYSTEM FOR DATA TRANSACTIONS ON A COMMUNICATIONS INTERFACE

HIGH PERFORMANCE INTERCONNECT

HIGH PERFORMANCE INTERCONNECT

HIGH PERFORMANCE INTERCONNECT

MULTICHIP PACKAGE LINK

MULTIPLE TRANSACTION DATA FLOW CONTROL UNIT FOR HIGH-SPEED INTERCON...

HIGH PERFORMANCE INTERCONNECT

MULTIPLE TRANSACTION DATA FLOW CONTROL UNIT FOR HIGH-SPEED INTERCON...

PROVIDING MULTI-SOCKET MEMORY COHERENCY USING CROSS-SOCKET SNOOP FI...

MULTICHIP PACKAGE LINK

MULTISLOT LINK LAYER FLIT WHEREIN FLIT INCLUDES THREE OR MORE SLOTS...

HIGH PERFORMANCE INTERCONNECT LINK LAYER

SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...

HIGH PERFORMANCE INTERCONNECT LINK LAYER

HIGH PERFORMANCE INTERCONNECT

MULTICHIP PACKAGE LINK

MULTIPLE TRANSACTION DATA FLOW CONTROL UNIT FOR HIGH-SPEED INTERCON...

CROSS-DIE INTERFACE SNOOP OR GLOBAL OBSERVATION MESSAGE ORDERING

MULTISLOT LINK LAYER FLIT

HIGH PERFORMANCE INTERCONNECT LINK LAYER

SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...

HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL

MULTIPLE TRANSACTION DATA FLOW CONTROL UNIT FOR HIGH-SPEED INTERCON...

HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL

SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...