Robert Thompson

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Tualatin, OR, US

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Patents Grantslast 30 patents

Information Patent Grant
Techniques for placement in highly constrained architectures
- Patent number 8,739,103
- Issue date May 27, 2014
- Cypress Semiconductor Corporation
- Avijit Dutta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for at-speed testing of digital circuits
- Patent number 7,437,636
- Issue date Oct 14, 2008
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for at-speed testing of digital circuits
- Patent number 6,966,021
- Issue date Nov 15, 2005
- Janusz Rajski
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Method and apparatus for at-speed testing of digital circuits
- Publication number 20060064616
- Publication date Mar 23, 2006
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for at-speed testing of digital circuits
- Publication number 20030097614
- Publication date May 22, 2003
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING