Robert W. Fiordalice

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Barrier material formation in integrated circuit structures
- Patent number 7,446,416
- Issue date Nov 4, 2008
- KLA-Tencor Corporation
- Robert W. Fiordalice
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nano-electrode-array for integrated circuit interconnects
- Patent number 7,226,856
- Issue date Jun 5, 2007
- KLA-Tencor Technologies Corporation
- Sergey D. Lopatin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Barrier enhancement
- Patent number 6,949,457
- Issue date Sep 27, 2005
- KLA-Tencor Technologies Corporation
- Robert W. Fiordalice
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having a titanium-aluminum compound
- Patent number 6,218,733
- Issue date Apr 17, 2001
- Motorola Inc.
- Robert W. Fiordalice
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a semiconductor device
- Patent number 6,218,302
- Issue date Apr 17, 2001
- Motorola Inc.
- Gregor Braeckelmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Inert plasma gas surface cleaning process performed insitu with phy...
- Patent number 6,187,682
- Issue date Feb 13, 2001
- Motorola Inc.
- Dean J. Denning
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Process for fabricating a multilevel interconnect
- Patent number 6,077,768
- Issue date Jun 20, 2000
- Motorola, Inc.
- T. P. Ong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an interconnect structure
- Patent number 5,814,557
- Issue date Sep 29, 1998
- Motorola, Inc.
- Ramnath Venkatraman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of decreasing resistivity in an electrically conductive layer
- Patent number 5,801,098
- Issue date Sep 1, 1998
- Motorola, Inc.
- Robert Fiordalice
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating a metallized interconnect
- Patent number 5,783,485
- Issue date Jul 21, 1998
- Motorola, Inc.
- T. P. Ong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for providing trench isolation
- Patent number 5,677,231
- Issue date Oct 14, 1997
- Motorola, Inc.
- Papu D. Maniar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for providing trench isolation and borderless contact
- Patent number 5,652,176
- Issue date Jul 29, 1997
- Motorola, Inc.
- Papu D. Maniar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating a metallized interconnect structure in a se...
- Patent number 5,633,199
- Issue date May 27, 1997
- Motorola Inc.
- Robert W. Fiordalice
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating a collimated metal layer and contact struct...
- Patent number 5,580,823
- Issue date Dec 3, 1996
- Motorola, Inc.
- Rama I. Hegde
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method for forming inlaid interconnects in a semiconductor device
- Patent number 5,578,523
- Issue date Nov 26, 1996
- Motorola, Inc.
- Robert W. Fiordalice
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a plug and semiconductor device having the same
- Patent number 5,534,462
- Issue date Jul 9, 1996
- Motorola, Inc.
- Robert W. Fiordalice
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making a semiconductor device having anti-reflective coa...
- Patent number 5,525,542
- Issue date Jun 11, 1996
- Motorola, Inc.
- Papu D. Maniar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating a metallization structure in a semiconducto...
- Patent number 5,429,989
- Issue date Jul 4, 1995
- Motorola, Inc.
- Robert W. Fiordalice
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a conductive interconnect in an integrated circuit
- Patent number 5,420,072
- Issue date May 30, 1995
- Motorola, Inc.
- Robert W. Fiordalice
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming copper interconnect structure
- Patent number 5,391,517
- Issue date Feb 21, 1995
- Motorola Inc.
- Avgerinos V. Gelatos
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming a sputter deposited metal film
- Patent number 5,358,615
- Issue date Oct 25, 1994
- Motorola, Inc.
- Leroy Grant
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Process for forming an intermetallic layer
- Patent number 5,358,901
- Issue date Oct 25, 1994
- Motorola, Inc.
- Robert W. Fiordalice
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
NANO-ELECTRODE-ARRAY FOR INTEGRATED CIRCUIT INTERCONNECTS
- Publication number 20070284746
- Publication date Dec 13, 2007
- KLA-Tencor Technologies Corporation
- Sergey D. Lopatin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Barrier enhancement
- Publication number 20050212138
- Publication date Sep 29, 2005
- KLA-Tencor Technologies Corporation
- Robert W. Fiordalice
- H01 - BASIC ELECTRIC ELEMENTS

Robert W. Fiordalice

Person

Patents Grantslast 30 patents

Barrier material formation in integrated circuit structures

Nano-electrode-array for integrated circuit interconnects

Barrier enhancement

Semiconductor device having a titanium-aluminum compound

Method for forming a semiconductor device

Inert plasma gas surface cleaning process performed insitu with phy...

Process for fabricating a multilevel interconnect

Method of forming an interconnect structure

Method of decreasing resistivity in an electrically conductive layer

Process for fabricating a metallized interconnect

Method for providing trench isolation

Method for providing trench isolation and borderless contact

Process for fabricating a metallized interconnect structure in a se...

Process for fabricating a collimated metal layer and contact struct...

Method for forming inlaid interconnects in a semiconductor device

Method for forming a plug and semiconductor device having the same

Method for making a semiconductor device having anti-reflective coa...

Process for fabricating a metallization structure in a semiconducto...

Method for forming a conductive interconnect in an integrated circuit

Process for forming copper interconnect structure

Process for forming a sputter deposited metal film

Process for forming an intermetallic layer

Patents Applicationslast 30 patents

NANO-ELECTRODE-ARRAY FOR INTEGRATED CIRCUIT INTERCONNECTS

Barrier enhancement