Roberto Ravasio

Person

Presezzo(BG), IT

People

Patents Grantslast 30 patents

Information Patent Grant
Method for performing error corrections of digital information codi...
- Patent number 10,630,317
- Issue date Apr 21, 2020
- Micron Technology, Inc.
- Massimiliano Lunelli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for performing error corrections of digital information codi...
- Patent number 8,966,335
- Issue date Feb 24, 2015
- Micron Technology, Inc.
- Massimiliano Lunelli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configuration of a multilevel flash memory device
- Patent number 8,572,361
- Issue date Oct 29, 2013
- Micron Technology, Inc.
- Angelo Bovino
- G11 - INFORMATION STORAGE
Information Patent Grant
Reading method of a memory device with embedded error-correcting co...
- Patent number 8,347,201
- Issue date Jan 1, 2013
- Micron Technology, Inc.
- Alessia Marelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile, electrically-programmable memory
- Patent number 8,065,467
- Issue date Nov 22, 2011
- Hynix Semiconductor Inc.
- Rino Micheloni
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method providing logic connections for data transfer
- Patent number 7,940,575
- Issue date May 10, 2011
- Qimonda AG
- Roberto Ravasio
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Configuration of a multi-level flash memory device
- Patent number 7,937,576
- Issue date May 3, 2011
- Micron Technology, Inc.
- Angelo Bovino
- G11 - INFORMATION STORAGE
Information Patent Grant
Reading method of a memory device with embedded error-correcting co...
- Patent number 7,908,543
- Issue date Mar 15, 2011
- Alessia Marelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit having a memory cell arrangement and method for...
- Patent number 7,800,943
- Issue date Sep 21, 2010
- Qimonda AG
- Roberto Ravasio
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Integrated memory system
- Patent number 7,730,357
- Issue date Jun 1, 2010
- Rino Micheloni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of programming cells of a NAND memory device
- Patent number 7,719,894
- Issue date May 18, 2010
- Luca Crippa
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with embedded error correction codes
- Patent number 7,581,153
- Issue date Aug 25, 2009
- Rino Micheloni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for compacting the erased threshold voltage distribution of...
- Patent number 7,529,136
- Issue date May 5, 2009
- Rino Micheloni
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory device with NAND architecture with reduced capacitive...
- Patent number 7,394,694
- Issue date Jul 1, 2008
- STMicroelectronics S.r.l.
- Rino Micheloni
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for accessing a multilevel nonvolatile memory device of the...
- Patent number 7,382,660
- Issue date Jun 3, 2008
- STMicroelectronics S.r.l.
- Angelo Bovino
- G11 - INFORMATION STORAGE
Information Patent Grant
Double page programming system and method
- Patent number 7,366,014
- Issue date Apr 29, 2008
- STMicroelectronics S.r.l.
- Rino Micheloni
- G11 - INFORMATION STORAGE
Information Patent Grant
NAND flash memory with erase verify based on shorter evaluation time
- Patent number 7,362,616
- Issue date Apr 22, 2008
- STMicroelectronics S.r.l.
- Angelo Bovino
- G11 - INFORMATION STORAGE
Information Patent Grant
Page buffer circuit and method for multi-level NAND programmable me...
- Patent number 7,336,538
- Issue date Feb 26, 2008
- STMicroelectronics S.r.l.
- Luca Crippa
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for performing error corrections of digital information codi...
- Patent number 7,328,397
- Issue date Feb 5, 2008
- STMicroelectronics, S.R.L.
- Massimiliano Lunelli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory system comprising a semiconductor memory
- Patent number 7,221,602
- Issue date May 22, 2007
- STMicroelectronics S.r.l.
- Rino Micheloni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and device for programming an electrically programmable non-...
- Patent number 7,068,540
- Issue date Jun 27, 2006
- STMicroelectronics S.r.l.
- Rino Micheloni
- G11 - INFORMATION STORAGE
Information Patent Grant
Non volatile memory device including a predetermined number of sectors
- Patent number 7,035,142
- Issue date Apr 25, 2006
- STMicroelectronics S.r.l.
- Osama Khouri
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and device for programming an electrically programmable non-...
- Patent number 7,031,193
- Issue date Apr 18, 2006
- STMicroelectronics S.r.l.
- Rino Micheloni
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for error control in multilevel cells with configurable numb...
- Patent number 7,017,099
- Issue date Mar 21, 2006
- STMicroelectronics S.r.l.
- Rino Micheloni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for programming a non-volatile memory device with adaptive...
- Patent number 6,956,773
- Issue date Oct 18, 2005
- STMicroelectronics S.r.l.
- Rino Micheloni
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR PERFORMING ERROR CORRECTIONS OF DIGITAL INFORMATION CODI...
- Publication number 20150143206
- Publication date May 21, 2015
- Micron Technology, Inc.
- Massimiliano Lunelli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
READING METHOD OF A MEMORY DEVICE WITH EMBEDDED ERROR-CORRECTING CO...
- Publication number 20110167318
- Publication date Jul 7, 2011
- Micron Technology, Inc.
- Alessia Marelli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURATION OF A MULTILEVEL FLASH MEMORY DEVICE
- Publication number 20110167206
- Publication date Jul 7, 2011
- Micron Technology, Inc.
- Angelo Bovino
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Device and Method Providing Logic Connections for Data Transfer
- Publication number 20090244949
- Publication date Oct 1, 2009
- Roberto Ravasio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Having a Memory Cell Arrangement and Method for...
- Publication number 20090185425
- Publication date Jul 23, 2009
- Roberto Ravasio
- G11 - INFORMATION STORAGE
Information Patent Application
Method for performing error corrections of digital information codi...
- Publication number 20080104477
- Publication date May 1, 2008
- STMicroelectronics S.r.I
- Massimiliano Lunelli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
NAND FLASH MEMORY DEVICE WITH ECC PROTECTED RESERVED AREA FOR NON-V...
- Publication number 20080065937
- Publication date Mar 13, 2008
- STMicroelectronics S.r.I.
- Rino Micheloni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF FIXING A READ EVALUATION TIME OR THE DIFFERENCE BETWEEN A...
- Publication number 20080062767
- Publication date Mar 13, 2008
- STMicroelectronics S.r.l.
- Luca CRIPPA
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF PROGRAMMING CELLS OF A NAND MEMORY DEVICE
- Publication number 20080049511
- Publication date Feb 28, 2008
- STMicroelectronics S.r.I.
- LUCA CRIPPA
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE, ELECTRICALLY-PROGRAMMABLE MEMORY
- Publication number 20080052458
- Publication date Feb 28, 2008
- STMicroelectronics S.r.l.
- Rino Micheloni
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR COMPACTING THE ERASED THRESHOLD VOLTAGE DISTRIBUTION OF...
- Publication number 20080049521
- Publication date Feb 28, 2008
- STMicroelectronics S.r.l.
- Rino Micheloni
- G11 - INFORMATION STORAGE
Information Patent Application
Reading method of a memory device with embedded error-correcting co...
- Publication number 20070234164
- Publication date Oct 4, 2007
- STMicroelectronics S.r.l.
- Alessia Marelli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR ACCESSING A MULTILEVEL NONVOLATILE MEMORY DEVICE OF THE...
- Publication number 20070047299
- Publication date Mar 1, 2007
- STMicroelectronics S.r.l.
- Angelo Bovino
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURATION OF A MULTILEVEL FLASH MEMORY DEVICE
- Publication number 20070038852
- Publication date Feb 15, 2007
- STMicroelectronics S.r.l.
- Angelo Bovino
- G11 - INFORMATION STORAGE
Information Patent Application
Page buffer circuit and method for multi-level NAND programmable me...
- Publication number 20070030735
- Publication date Feb 8, 2007
- Luca Crippa
- G11 - INFORMATION STORAGE
Information Patent Application
Double page programming system and method
- Publication number 20070030732
- Publication date Feb 8, 2007
- Rino Micheloni
- G11 - INFORMATION STORAGE
Information Patent Application
Nand flash memory with erase verify based on shorter evaluation time
- Publication number 20070030730
- Publication date Feb 8, 2007
- STMicroelectronics S.r.I.
- Angelo Bovino
- G11 - INFORMATION STORAGE
Information Patent Application
Flash memory device with NAND architecture with reduced capacitive...
- Publication number 20060285387
- Publication date Dec 21, 2006
- STMicroelectronics S.r.l.
- Rino Micheloni
- G11 - INFORMATION STORAGE
Information Patent Application
Memory with embedded error correction codes
- Publication number 20060059406
- Publication date Mar 16, 2006
- STMicroelectronics S.r.l.
- Rino Micheloni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for correcting low latency errors in read and wri...
- Publication number 20060010363
- Publication date Jan 12, 2006
- STMicroelectronics S.r.l.
- Alessia Marelli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and system for correcting errors in electronic memory devices
- Publication number 20060005109
- Publication date Jan 5, 2006
- STMicroelectronics S.r.l.
- Alessia Marelli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method for performing error corrections of digital information codi...
- Publication number 20050050434
- Publication date Mar 3, 2005
- Massimiliano Lunelli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Integrated memory system
- Publication number 20040230869
- Publication date Nov 18, 2004
- STMicroelectronics S.r.I.
- Rino Micheloni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory system comprising a semiconductor memory
- Publication number 20040181643
- Publication date Sep 16, 2004
- STMicroelectronics S.r.l.
- Rino Micheloni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Non volatile memory device including a predetermined number of sectors
- Publication number 20040170057
- Publication date Sep 2, 2004
- STMicroelectronics S.r.l.
- Osama Khouri
- G11 - INFORMATION STORAGE
Information Patent Application
Method and device for programming an electrically programmable non-...
- Publication number 20040170061
- Publication date Sep 2, 2004
- STMicroelectronics S.r.l.
- Rino Micheloni
- G11 - INFORMATION STORAGE
Information Patent Application
Method and device for programming an electrically programmable non-...
- Publication number 20040170062
- Publication date Sep 2, 2004
- STMICROELCTRONICS S.r.l
- Rino Micheloni
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit for programming a non-volatile memory device with adaptive...
- Publication number 20040145947
- Publication date Jul 29, 2004
- STMicroelectronics S.r.l.
- Rino Micheloni
- G11 - INFORMATION STORAGE
Information Patent Application
Method for error control in multilevel cells with configurable numb...
- Publication number 20030018861
- Publication date Jan 23, 2003
- STMicroelectronics S.r. I.
- Rino Micheloni
- G06 - COMPUTING CALCULATING COUNTING

Roberto Ravasio

Person

Patents Grantslast 30 patents

Method for performing error corrections of digital information codi...

Method for performing error corrections of digital information codi...

Configuration of a multilevel flash memory device

Reading method of a memory device with embedded error-correcting co...

Non-volatile, electrically-programmable memory

Memory device and method providing logic connections for data transfer

Configuration of a multi-level flash memory device

Reading method of a memory device with embedded error-correcting co...

Integrated circuit having a memory cell arrangement and method for...

Integrated memory system

Method of programming cells of a NAND memory device

Memory with embedded error correction codes

Method for compacting the erased threshold voltage distribution of...

Flash memory device with NAND architecture with reduced capacitive...

Method for accessing a multilevel nonvolatile memory device of the...

Double page programming system and method

NAND flash memory with erase verify based on shorter evaluation time

Page buffer circuit and method for multi-level NAND programmable me...

Method for performing error corrections of digital information codi...

Memory system comprising a semiconductor memory

Method and device for programming an electrically programmable non-...

Non volatile memory device including a predetermined number of sectors

Method and device for programming an electrically programmable non-...

Method for error control in multilevel cells with configurable numb...

Circuit for programming a non-volatile memory device with adaptive...

Patents Applicationslast 30 patents

METHOD FOR PERFORMING ERROR CORRECTIONS OF DIGITAL INFORMATION CODI...

READING METHOD OF A MEMORY DEVICE WITH EMBEDDED ERROR-CORRECTING CO...

CONFIGURATION OF A MULTILEVEL FLASH MEMORY DEVICE

Memory Device and Method Providing Logic Connections for Data Transfer

Integrated Circuit Having a Memory Cell Arrangement and Method for...

Method for performing error corrections of digital information codi...

NAND FLASH MEMORY DEVICE WITH ECC PROTECTED RESERVED AREA FOR NON-V...

METHOD OF FIXING A READ EVALUATION TIME OR THE DIFFERENCE BETWEEN A...

METHOD OF PROGRAMMING CELLS OF A NAND MEMORY DEVICE

NON-VOLATILE, ELECTRICALLY-PROGRAMMABLE MEMORY

METHOD FOR COMPACTING THE ERASED THRESHOLD VOLTAGE DISTRIBUTION OF...

Reading method of a memory device with embedded error-correcting co...

METHOD FOR ACCESSING A MULTILEVEL NONVOLATILE MEMORY DEVICE OF THE...

CONFIGURATION OF A MULTILEVEL FLASH MEMORY DEVICE

Page buffer circuit and method for multi-level NAND programmable me...

Double page programming system and method

Nand flash memory with erase verify based on shorter evaluation time

Flash memory device with NAND architecture with reduced capacitive...

Memory with embedded error correction codes

Method and system for correcting low latency errors in read and wri...

Method and system for correcting errors in electronic memory devices

Method for performing error corrections of digital information codi...

Integrated memory system

Memory system comprising a semiconductor memory

Non volatile memory device including a predetermined number of sectors

Method and device for programming an electrically programmable non-...

Method and device for programming an electrically programmable non-...

Circuit for programming a non-volatile memory device with adaptive...

Method for error control in multilevel cells with configurable numb...