METHOD OF PROGRAMMING CELLS OF A NAND MEMORY DEVICE

Abstract

The capacitive coupling between two adjacent bitlines of a NAND memory device may be exploited for boosting the voltage of bitlines that are not to be programmed in order to inhibit program operations on them. The even (odd) bitlines that include cells not to be programmed are biased with a first voltage for inhibiting them from being programmed while the even (odd) bitlines that include cells to be programmed are grounded. The adjacent odd (even) bitlines are biased at the supply voltage or at an auxiliary voltage for boosting the bias voltage of the even (odd) bitlines above the supply voltage. The bias voltage of the even (odd) bitlines that include cells not to be programmed is boosted because of the relevant parasitic coupling capacitances between adjacent bitlines.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described referring to the attached drawings, wherein:

FIG. 1 depicts two bitlines of a NAND memory device and a page buffer connected to them according to the prior art;

FIG. 2 illustrates the Gray coding for a four-level memory cell according to the prior art;

FIG. 3 depicts schematically a NAND memory device with highlighted electrical paths that are active while precharging the bitline according to the prior art;

FIG. 4 shows timing diagrams of the main signals of the device of FIG. 3 during a program operation;

FIG. 5 is similar to FIG. 3 and illustrates the bitline selective discharge step;

FIG. 6 shows the parasitic capacitances between the central bitline and the various parts of the memory device according to the present invention;

FIG. 7 is a timing graph of the main signals of the memory device during a program operation according to a first embodiment of the present invention;

FIGS. 8 to 10 illustrate various steps of a first embodiment of the method according to the present invention;

FIGS. 11 and 12 illustrate various steps of a second embodiment of the method according to the present invention; and

FIG. 13 is a timing graph of the main signals of the memory device during a program operation according to a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

For ease of comparison with the prior art, the invention will be described for the case of a FLASH NAND memory device. There is a way of biasing the bitlines that are not to be programmed with a boosted voltage larger than the supply voltage VDD without using charge pump generators or increasing program times. This may be obtained by exploiting the coupling capacitances between adjacent bitlines. Coupling capacitances among a bitline and the two bitlines adjacent thereto are almost 80% of the total capacitance of the bitline (FIG. 6).

A main difference between the illustrated method of programming a memory cell of a NAND memory device is that not all the bitlines are programmed at the same time, but the cells of the even (odd) bitlines are programmed before the odd (even) bitlines. Of course, the roles of the even and the odd bitlines may be exchanged between them.

A sample timing of the main signals of the memory device when programming according to a first embodiment of the method is depicted in FIG. 7. Referring to FIG. 8, suppose that the cells of the even bitlines are programmed first. In this situation, the odd bitlines and the even bitlines that include cells to be programmed are grounded (DISCHE and VIRPWR are grounded, while DISCHO is at a boosted voltage HV for discharging the odd bitlines), otherwise they are biased with a voltage VDD-VTH if they include cells not to be programmed.

This last operation is carried out by connecting the bitlines to be biased to the respective output node of the page buffer PB through the signals SELBLE.

At the end of the transient for biasing the even bitlines at the voltage VDD-VTH, the node VIRPWR is brought to the supply voltage VDD. The odd bitlines are brought to the voltage VDD because the signal DISCHO is still high and at the same time the bias voltage of the even bitlines is boosted (FIG. 9) because of the coupling capacitances between the even and the odd bitlines. Therefore, the bias voltage VDD-VTH is increased by a voltage equal to about 80% of the supply voltage, that is, the even bitlines are biased with a voltage Vboost: Vboost=VDD−VTH+0.8*VDD.

Also, the even bitlines that include cells to be programmed (that should remain grounded) will be biased with a certain voltage, but they will discharge immediately through the transistor SELBLE.

If, for example, the supply voltage VDD is 2.5V and VTH is 1V, the boosted voltage Vboost is 3.5V. If the supply voltage VDD was 3.8V, the boosted voltage Vboost would be 5.8V. The above examples demonstrate that it is possible to increase the bias voltage of bitlines not to be programmed with a boosted voltage sufficient to prevent undesired programming operations. Therefore, it is not necessary to use dedicated charge pump generators or increase the programming times.

It is possible to obtain an even larger boosted voltage if the memory already includes a charge pump that generates the voltage Vsurv by biasing the node VIRPWR with the voltage Vsurv instead of the supply voltage VDD, thus obtaining Vboost=VDD−VTH+0.8*Vsurv. Once the cells that are not to be programmed are at a boost bias voltage, program pulses WL are provided to the cells of a selected wordline.

As a less preferred alternative, the even bitlines that include cells not to be programmed may be biased with a voltage smaller than the supply voltage VDD and the adjacent odd bitlines also with a voltage smaller than the supply voltage, provided that the bias voltage of the even bitlines is boosted above the supply voltage for inhibiting them from being programmed.

According to a second embodiment, it is possible to increase the boosted voltage Vboost by VTH. The even bitlines are biased with the voltage VDD through the signals DISCHE when the line VIRPWR is at the supply voltage VDD (FIG. 10). The odd bitlines are grounded by turning on the respective selection switches through the signals SELBLO (DISCHO is off) and making the page buffer keep at a ground potential the respective output node SO. Therefore, the odd bitlines are grounded while the even bitlines are biased with the voltage VDD and not with the voltage VDD-VTH, because the even bitlines are biased by the line VIRPWR and not by the page buffer.

All the switches SELBLx are switched on and the page buffer biases all the bitlines with the voltage VDD if they are not to be programmed or with the ground potential in the opposite case. By opening the selector switches SELBLE the even bitlines are discharged (FIG. 11) depending on whether or not they include cells to be programmed.

At this point, only the bitlines to be programmed are grounded. Thus (FIG. 12) the bias voltage of the even bitlines is boosted by switching on the switch DISCHO (the node VIRPWR is already at the supply voltage VDD). The boosted voltage is: Vboost=VDD+0.8*VDD.

The boosted voltage is larger than the previous case because the bitlines not to be programmed are biased through the selector DISCHE and not by the page buffer through the signal SELBLE. Finally, program pulses WL are distributed to the cells of a selected wordline. A sample timing diagram of the main signals while executing the method steps of this other embodiment is depicted in FIG. 13. This is self-explanatory for those skilled in the art and will not be illustrated further.

As in the previous embodiment, if a charge pump voltage generator is available in the memory device, it is possible to bias the odd bitlines with the voltage Vsurv generated by it, thus Vboost=VDD+0.8*Vsurv. The larger the scaling down of the size of memory devices, the more relevant the coupling capacitances between adjacent bitlines, and thus the illustrated method is more effective.

Claims

1-6. (canceled)

7. A method of programming selected memory cells of a NAND memory device while protecting deselected memory cells from being programmed, the NAND memory device comprising an array of memory cells coupled to bitlines and wordlines, the method comprising: biasing first bitlines that include memory cells not to be programmed at a first voltage, each biased first bitline being inhibited from receiving program pulses;biasing successively second adjacent bitlines at a second voltage for boosting, above a supply voltage of the NAND memory device, the bias voltage of the first bitlines that include the memory cells not to be programmed;biasing at a reference potential bitlines that include memory cells to be programmed for letting the bitlines receive program pulses; andgenerating the program pulses to the first bitlines biased at the first voltage.

8. The method of claim 7, wherein the first bitlines are even bitlines, and the second adjacent bitlines are odd bitlines.

9. The method of claim 7, wherein the second voltage is either the supply voltage of the NAND memory device or an auxiliary voltage.

10. The method of claim 7, wherein the program pulses are generated in parallel.

11. The method of claim 7, wherein the first voltage is the supply voltage of the NAND memory device.

12. The method of claim 9, wherein the NAND memory device comprises a charge pump voltage generator that supplies a boosted voltage, and wherein the auxiliary voltage is the boosted voltage.

13. The method of claim 7, wherein the NAND memory device comprises a respective selection switch coupled to each bitline, and wherein the memory cells corresponding to the first bitlines that are not to be programmed are biased at the supply voltage of the NAND memory device by turning on the corresponding selection switches that connect the bitlines to the supply voltage.

14. The method of claim 10, wherein the NAND memory device further comprises a respective page buffer coupled to each bitline, each page buffer comprising an output node in which the supply voltage and the reference potential are alternatively replicated, each first bitline that is not to be programmed is biased at the supply voltage by turning on the corresponding selection switch that connects the bitline to the output node of the page buffer when at the supply voltage.

15. The method of claim 7, further comprising preventively biasing all the bitlines at the supply voltage of the NAND memory device, then biasing at the reference potential the bitlines that include memory cells that are not to be programmed and the second adjacent bitlines.

16. A method of programming a memory device comprising an array of memory cells, and bitlines and wordlines coupled to the array of memory cells, the method comprising: biasing first bitlines that include memory cells not to be programmed at a first voltage, each biased first bitline being inhibited from receiving program pulses;biasing successively second adjacent bitlines at a second voltage for boosting, above a supply voltage of the memory device, the bias voltage of the first bitlines that include the memory cells not to be programmed;biasing at a reference potential bitlines that include memory cells to be programmed for letting the bitlines receive program pulses; andgenerating the program pulses to the first bitlines biased at the first voltage.

17. The method of claim 16, wherein the first bitlines are even bitlines, and the second adjacent bitlines are odd bitlines.

18. The method of claim 16, wherein the second voltage is either the supply voltage of the memory device or an auxiliary voltage.

19. The method of claim 16, wherein the program pulses are generated in parallel.

20. The method of claim 16, wherein the first voltage is the supply voltage of the memory device.

21. The method of claim 18, wherein the memory device comprises a charge pump voltage generator that supplies a boosted voltage, and wherein the auxiliary voltage is the boosted voltage.

22. The method of claim 16, wherein the memory device comprises a respective selection switch coupled to each bitline, and wherein the memory cells corresponding to the first bitlines that are not to be programmed are biased at the supply voltage of the memory device by turning on the corresponding selection switches that connect the bitlines to the supply voltage.

23. The method of claim 22, wherein the memory device further comprises a respective page buffer coupled to each bitline, each page buffer comprising an output node in which the supply voltage and the reference potential are alternatively replicated, each first bitline that is not to be programmed is biased at the supply voltage by turning on the corresponding selection switch that connects the bitline to the output node of the page buffer when at the supply voltage.

24. The method of claim 16, further comprising preventively biasing all the bitlines at the supply voltage of the memory device, then biasing at the reference potential the bitlines that include memory cells that are not to be programmed and the second adjacent bitlines.

25. A memory device comprising: an array of memory cells;bitlines coupled to said array of memory cells, said bitlines including first bitlines, and second bitlines adjacent to said first bitlines;wordlines coupled to said array of memory cells;a supply line coupled to said array of memory cells for providing a supply voltage thereto;biasing circuits coupled to said bitlines for performing at least the following biasing said first bitlines that include memory cells not to be programmed at a first voltage, each biased first bitline being inhibited from receiving program pulses;biasing successively said second adjacent bitlines at a second voltage for boosting, above the supply voltage, the bias voltage of said first bitlines that include said memory cells not to be programmed;biasing at a reference potential bitlines that include memory cells to be programmed for letting said bitlines receive program pulses; anda programming circuit for generating the program pulses to said first bitlines biased at the first voltage.

26. The memory device of claim 25, wherein said first bitlines are even bitlines, and said second adjacent bitlines are odd bitlines.

27. The memory device of claim 25, wherein the second voltage is either the supply voltage or an auxiliary voltage.

28. The memory device of claim 25, wherein the program pulses are generated in parallel.

29. The memory device of claim 25, wherein the first voltage is the supply voltage.

30. The memory device of claim 27, further comprising a charge pump voltage generator that supplies a boosted voltage, and wherein the auxiliary voltage is the boosted voltage.

31. The memory device of claim 25, further comprising a respective selection switch coupled to each bitline, and wherein said memory cells corresponding to said first bitlines that are not to be programmed are biased at the supply voltage by turning on said corresponding selection switches that connect said bitlines to the supply voltage.

32. The memory device of claim 31, further comprising a respective page buffer coupled to each bitline, each page buffer comprising an output node in which the supply voltage and the reference potential are alternatively replicated, said first bitlines that are not to be programmed are biased at the supply voltage by turning on said corresponding selection switch that connects said bitline to the output node of said page buffer when at the supply voltage.

33. The memory device of claim 25, wherein said bias circuits also preventively bias all of said bitlines at the supply voltage, then bias at the reference potential said bitlines that include memory cells that are not to be programmed and said second adjacent bitlines.

34. The memory device of claim 25, wherein said array of memory cells is configured so that the memory device is a NAND memory device.