Roger D. Norwood

Person

Stafford, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatuses and methods for address detection
- Patent number 11,217,295
- Issue date Jan 4, 2022
- Micron Technology, Inc.
- Kallol Mazumder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for address detection
- Patent number 10,534,686
- Issue date Jan 14, 2020
- Micron Technology, Inc.
- Kallol Mazumder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous interface circuit and method for a pseudo-static memor...
- Patent number 7,106,637
- Issue date Sep 12, 2006
- Micron Technology, Inc.
- Simon J. Lovett
- G11 - INFORMATION STORAGE
Information Patent Grant
Asynchronous interface circuit and method for a pseudo-static memor...
- Patent number 6,690,606
- Issue date Feb 10, 2004
- Micron Technology, Inc.
- Simon J. Lovett
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiplexed noisy-quiet power busing for improved area efficiencies...
- Patent number 6,219,294
- Issue date Apr 17, 2001
- Micron Technology, Inc.
- Brian W. Huber
- G11 - INFORMATION STORAGE
Information Patent Grant
High-speed memory arranged for operating synchronously with a micro...
- Patent number 6,088,280
- Issue date Jul 11, 2000
- Texas Instruments Incorporated
- Wilbur Christian Vogley
- G11 - INFORMATION STORAGE
Information Patent Grant
Internal clock multiplication for test time reduction
- Patent number 6,069,829
- Issue date May 30, 2000
- Texas Instruments Incorporated
- Yutaka Komai
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock skew circuit
- Patent number 6,049,241
- Issue date Apr 11, 2000
- Texas Instruments Incorporated
- Brian L. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed memory arranged for operating synchronously with a micro...
- Patent number 5,982,694
- Issue date Nov 9, 1999
- Texas Instruments Incorporated
- Wilbur Christian Vogley
- G11 - INFORMATION STORAGE
Information Patent Grant
Data processing system arranged for operating synchronously with a...
- Patent number 5,912,854
- Issue date Jun 15, 1999
- Texas Instruments Incorporated
- Wilbur Christian Vogley
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory access circuits for test time reduction
- Patent number 5,910,923
- Issue date Jun 8, 1999
- Texas Instruments Incorporated
- Brian L. Brown
- G11 - INFORMATION STORAGE
Information Patent Grant
Random access memory with latency arranged for operating synchronou...
- Patent number 5,808,958
- Issue date Sep 15, 1998
- Texas Instruments Incorporated
- Wilbur Christian Vogley
- G11 - INFORMATION STORAGE
Information Patent Grant
Random access memory arranged for operating synchronously with a mi...
- Patent number 5,587,954
- Issue date Dec 24, 1996
- Texas Instruments Incorporated
- Wilbur C. Vogley
- G11 - INFORMATION STORAGE
Information Patent Grant
Interface level programmability
- Patent number 5,557,219
- Issue date Sep 17, 1996
- Texas Instruments Incorporated
- Roger D. Norwood
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for inhibiting a predecoder when selecting a r...
- Patent number 5,475,640
- Issue date Dec 12, 1995
- Texas Instruments Incorporated
- David V. Kersh
- G11 - INFORMATION STORAGE
Information Patent Grant
System including a data processor, a synchronous dram, a peripheral...
- Patent number 5,390,149
- Issue date Feb 14, 1995
- Texas Instruments Incorporated
- Wilbur C. Vogley
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual receiver edge-triggered digital signal level detection system
- Patent number 5,347,184
- Issue date Sep 13, 1994
- Texas Instruments Incorporated
- Michael C. Stephens
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for inhibiting a predecoder when selecting a r...
- Patent number 5,327,380
- Issue date Jul 5, 1994
- Texas Instruments Incorporated
- David V. Kersh
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for generating power-up pulse
- Patent number 5,203,867
- Issue date Apr 20, 1993
- Texas Instruments Incorporated
- Andrew M. Love
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Boot-strapped decoder circuit
- Patent number 5,166,554
- Issue date Nov 24, 1992
- Chitranjan N. Reddy
- G11 - INFORMATION STORAGE
Information Patent Grant
Power-up pulse generator circuit
- Patent number 5,030,845
- Issue date Jul 9, 1991
- Texas Instruments Incorporated
- Andrew M. Love
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit furnishing a segmented input circuit
- Patent number 5,010,260
- Issue date Apr 23, 1991
- Texas Instruments Incorporated
- Roger D. Norwood
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor dynamic memory device with metal-level selection of p...
- Patent number 5,001,673
- Issue date Mar 19, 1991
- Texas Instruments Incorporated
- Roger D. Norwood
- G11 - INFORMATION STORAGE
Information Patent Grant
Distributed signal transmission to an integrated circuit array
- Patent number 4,969,123
- Issue date Nov 6, 1990
- Texas Instruments Incorporated
- Roger D. Norwood
- G11 - INFORMATION STORAGE
Information Patent Grant
Glitch suppression circuit
- Patent number 4,965,474
- Issue date Oct 23, 1990
- Texas Instruments Incorporated
- Jimmie D. Childers
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor dynamic memory device with metal-level selection of p...
- Patent number 4,876,671
- Issue date Oct 24, 1989
- Texas Instruments Incorporated
- Roger D. Norwood
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed, low-power nibble mode circuitry for dynamic memory
- Patent number 4,685,089
- Issue date Aug 4, 1987
- Texas Instruments Incorporated
- Pravin P. Patel
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor dynamic memory device with decoded active loads
- Patent number 4,656,613
- Issue date Apr 7, 1987
- Texas Instruments Incorporated
- Roger D. Norwood
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor dynamic memory device with multiplexed sense amplifie...
- Patent number 4,636,987
- Issue date Jan 13, 1987
- Texas Instruments
- Roger D. Norwood
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
APPARATUSES AND METHODS FOR ADDRESS DETECTION
- Publication number 20200042423
- Publication date Feb 6, 2020
- Micron Technology, Inc.
- Kallol Mazumder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR ADDRESS DETECTION
- Publication number 20150213872
- Publication date Jul 30, 2015
- Micron Technology, Inc.
- Kallol Mazumder
- G11 - INFORMATION STORAGE
Information Patent Application
Asynchronous interface circuit and method for a pseudo-static memor...
- Publication number 20040141397
- Publication date Jul 22, 2004
- Simon J. Lovett
- G11 - INFORMATION STORAGE
Information Patent Application
Asynchronous interface circuit and method for a pseudo-static memor...
- Publication number 20030179612
- Publication date Sep 25, 2003
- Simon J. Lovett
- G11 - INFORMATION STORAGE

Roger D. Norwood

Person

Patents Grantslast 30 patents

Apparatuses and methods for address detection

Apparatuses and methods for address detection

Asynchronous interface circuit and method for a pseudo-static memor...

Asynchronous interface circuit and method for a pseudo-static memor...

Multiplexed noisy-quiet power busing for improved area efficiencies...

High-speed memory arranged for operating synchronously with a micro...

Internal clock multiplication for test time reduction

Clock skew circuit

High speed memory arranged for operating synchronously with a micro...

Data processing system arranged for operating synchronously with a...

Memory access circuits for test time reduction

Random access memory with latency arranged for operating synchronou...

Random access memory arranged for operating synchronously with a mi...

Interface level programmability

Method and apparatus for inhibiting a predecoder when selecting a r...

System including a data processor, a synchronous dram, a peripheral...

Dual receiver edge-triggered digital signal level detection system

Method and apparatus for inhibiting a predecoder when selecting a r...

Method for generating power-up pulse

Boot-strapped decoder circuit

Power-up pulse generator circuit

Integrated circuit furnishing a segmented input circuit

Semiconductor dynamic memory device with metal-level selection of p...

Distributed signal transmission to an integrated circuit array

Glitch suppression circuit

Semiconductor dynamic memory device with metal-level selection of p...

High speed, low-power nibble mode circuitry for dynamic memory

Semiconductor dynamic memory device with decoded active loads

Semiconductor dynamic memory device with multiplexed sense amplifie...

Patents Applicationslast 30 patents

APPARATUSES AND METHODS FOR ADDRESS DETECTION

APPARATUSES AND METHODS FOR ADDRESS DETECTION

Asynchronous interface circuit and method for a pseudo-static memor...

Asynchronous interface circuit and method for a pseudo-static memor...