Roger I. Kung

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Synchronous memory having parallel output data paths
- Patent number 5,402,389
- Issue date Mar 28, 1995
- Motorola, Inc.
- Stephen T. Flannagan
- G11 - INFORMATION STORAGE
Information Patent Grant
CMOS dynamic random-access memory with active cycle one half power...
- Patent number 4,584,672
- Issue date Apr 22, 1986
- Intel Corporation
- Joseph D. Schutz
- G11 - INFORMATION STORAGE
Information Patent Grant
Output buffer with voltage sustainer circuit
- Patent number RE31662
- Issue date Sep 4, 1984
- Motorola, Inc.
- Roger I. Kung
- 307 - Electrical transmission or interconnection systems
Information Patent Grant
Dynamic output buffer
- Patent number RE31663
- Issue date Sep 4, 1984
- Motorola, Inc.
- Roger I. Kung
- 307 - Electrical transmission or interconnection systems
Information Patent Grant
Testing method and apparatus for dram
- Patent number 4,468,759
- Issue date Aug 28, 1984
- Intel Corporation
- Roger I. Kung
- G11 - INFORMATION STORAGE
Information Patent Grant
Byte-wide dynamic RAM with multiplexed internal buses
- Patent number 4,449,207
- Issue date May 15, 1984
- Intel Corporation
- Roger I. Kung
- G11 - INFORMATION STORAGE
Information Patent Grant
Signal generator having minimum delay
- Patent number 4,267,466
- Issue date May 12, 1981
- Motorola, Inc.
- Roger I. Kung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic output buffer
- Patent number 4,250,412
- Issue date Feb 10, 1981
- Motorola, Inc.
- Roger I. Kung
- G11 - INFORMATION STORAGE
Information Patent Grant
Write circuit for a read/write memory
- Patent number 4,202,045
- Issue date May 6, 1980
- Motorola, Inc.
- Roger I. Kung
- G11 - INFORMATION STORAGE

Roger I. Kung

Person

Patents Grantslast 30 patents

Synchronous memory having parallel output data paths

CMOS dynamic random-access memory with active cycle one half power...

Output buffer with voltage sustainer circuit

Dynamic output buffer

Testing method and apparatus for dram

Byte-wide dynamic RAM with multiplexed internal buses

Signal generator having minimum delay

Dynamic output buffer

Write circuit for a read/write memory