Roland Albert Béchade

Person

Somerville, NJ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Digital signal multiplier
- Patent number 6,415,008
- Issue date Jul 2, 2002
- Roland Albert Béchade
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Carry select adder using two level selectors
- Patent number 6,003,059
- Issue date Dec 14, 1999
- International Business Machines Corp.
- Roland A. Bechade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Zero and one detection chain for a carry select adder
- Patent number 5,975,749
- Issue date Nov 2, 1999
- International Business Machines Corporation
- Roland A. Bechade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimized, combined leading zeros counter and shifter
- Patent number 5,923,574
- Issue date Jul 13, 1999
- International Business Machines Corporation
- Roland Albert Bechade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
N-bit comparator using count leading 1 circuits
- Patent number 5,905,428
- Issue date May 18, 1999
- International Business Machines Corporation
- Roland A. Bechade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Least significant bit and guard bit extractor
- Patent number 5,841,683
- Issue date Nov 24, 1998
- International Business Machines Corporation
- Roland Albert Bechade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast 4-2 carry save adder using multiplexer logic
- Patent number 5,805,491
- Issue date Sep 8, 1998
- International Business Machines Corporation
- Roland A. Bechade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed multiplexer
- Patent number 5,789,966
- Issue date Aug 4, 1998
- International Business Machines Corporation
- Roland Albert Bechade
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed mask generation using selection logic
- Patent number 5,745,744
- Issue date Apr 28, 1998
- International Business Machines Corporation
- Roland Albert Bechade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for determining the amount of leading zeros or...
- Patent number 5,568,410
- Issue date Oct 22, 1996
- International Business Machines Corporation
- Roland A. Bechade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for store rounding and circuit therefor
- Patent number 5,511,016
- Issue date Apr 23, 1996
- International Business Machines Corporation
- Roland A. Bechade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transition-controlled off-chip driver
- Patent number 5,430,387
- Issue date Jul 4, 1995
- International Business Machines Corporation
- Roland A. Bechade
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiplier employing carry select or carry look-ahead adders in hie...
- Patent number 5,283,755
- Issue date Feb 1, 1994
- International Business Machines Corporation
- Roland A. Bechade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process independent digital clock signal shaping network
- Patent number 5,278,456
- Issue date Jan 11, 1994
- International Business Machines Corporation
- Roland A. Bechade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock signal latency elimination network
- Patent number 5,272,729
- Issue date Dec 21, 1993
- International Business Machines Corporation
- Roland Bechade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process independent digital clock signal shaping network
- Patent number 5,179,294
- Issue date Jan 12, 1993
- International Business Machines Corporation
- Roland A. Bechade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Plural dummy select chain logic synthesis network
- Patent number 4,982,357
- Issue date Jan 1, 1991
- International Business Machines Corporation
- Roland A. Bechade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pass gate multiplexer
- Patent number 4,912,339
- Issue date Mar 27, 1990
- International Business Machines Corporation
- Roland A. Bechade
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital binary array multipliers using inverting full adders
- Patent number 4,768,161
- Issue date Aug 30, 1988
- International Business Machines Corporation
- Roland A. Bechade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arithmetic logic circuit having a carry generator
- Patent number 4,766,565
- Issue date Aug 23, 1988
- International Business Machines Corporation
- Roland A. Bechade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for forming aligned interconnections between logic stages
- Patent number 4,742,019
- Issue date May 3, 1988
- International Business Machines Corporation
- Roland A. Bechade
- H01 - BASIC ELECTRIC ELEMENTS

Roland Albert Béchade

Person

Patents Grantslast 30 patents

Digital signal multiplier

Carry select adder using two level selectors

Zero and one detection chain for a carry select adder

Optimized, combined leading zeros counter and shifter

N-bit comparator using count leading 1 circuits

Least significant bit and guard bit extractor

Fast 4-2 carry save adder using multiplexer logic

Distributed multiplexer

High speed mask generation using selection logic

Method and apparatus for determining the amount of leading zeros or...

Method for store rounding and circuit therefor

Transition-controlled off-chip driver

Multiplier employing carry select or carry look-ahead adders in hie...

Process independent digital clock signal shaping network

Clock signal latency elimination network

Process independent digital clock signal shaping network

Plural dummy select chain logic synthesis network

Pass gate multiplexer

Digital binary array multipliers using inverting full adders

Arithmetic logic circuit having a carry generator

Method for forming aligned interconnections between logic stages