Ronald J. Syzdek

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Scalable split gate memory cell array
- Patent number 9,685,339
- Issue date Jun 20, 2017
- NXP USA, INC.
- Jane A. Yater
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Common source architecture for split gate memory
- Patent number 9,536,614
- Issue date Jan 3, 2017
- NXP USA, INC.
- Gilles J. Muller
- G11 - INFORMATION STORAGE
Information Patent Grant
Multibit sense amplifier calibration
- Patent number 9,218,889
- Issue date Dec 22, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Tahmina Akhter
- G11 - INFORMATION STORAGE
Information Patent Grant
Smart charge pump configuration for non-volatile memories
- Patent number 9,111,629
- Issue date Aug 18, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Jeffrey C. Cunningham
- G11 - INFORMATION STORAGE
Information Patent Grant
Biasing split gate memory cell during power-off mode
- Patent number 9,111,639
- Issue date Aug 18, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Cheong Min Hong
- G11 - INFORMATION STORAGE
Information Patent Grant
Sector-based regulation of program voltages for non-volatile memory...
- Patent number 9,013,927
- Issue date Apr 21, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Jeffrey C. Cunningham
- G11 - INFORMATION STORAGE
Information Patent Grant
Control gate word line driver circuit for multigate memory
- Patent number 8,971,147
- Issue date Mar 3, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Gilles Muller
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming a split gate bit cell
- Patent number 8,885,403
- Issue date Nov 11, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Cheong M. Hong
- G11 - INFORMATION STORAGE
Information Patent Grant
Configurable multistage charge pump using a supply detect scheme
- Patent number 8,704,587
- Issue date Apr 22, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Karthik Ramanan
- G11 - INFORMATION STORAGE
Information Patent Grant
Read conditions for a non-volatile memory (NVM)
- Patent number 8,310,877
- Issue date Nov 13, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Jeffrey C. Cunningham
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with adjustable read reference based on ECC and metho...
- Patent number 7,865,797
- Issue date Jan 4, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Richard K. Eguchi
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory with reduced charge fluence
- Patent number 7,843,730
- Issue date Nov 30, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Ronald J. Syzdek
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for electrically trimming an NVM reference cell
- Patent number 7,782,664
- Issue date Aug 24, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Horacio P. Gasquet
- G11 - INFORMATION STORAGE
Information Patent Grant
Read reference technique with current degradation protection
- Patent number 7,742,340
- Issue date Jun 22, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Fuchen Mu
- G11 - INFORMATION STORAGE
Information Patent Grant
Electronic device including a nonvolatile memory array and methods...
- Patent number 7,668,018
- Issue date Feb 23, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Ronald J. Syzdek
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit cell reference device and methods thereof
- Patent number 7,649,781
- Issue date Jan 19, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Ronald J. Syzdek
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming a memory device having error correction logic
- Patent number 7,624,329
- Issue date Nov 24, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Ronald J. Syzdek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with retained indicator of read reference level
- Patent number 7,564,716
- Issue date Jul 21, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Ronald J. Syzdek
- G11 - INFORMATION STORAGE
Information Patent Grant
Electrical erasable programmable memory transconductance testing
- Patent number 7,545,679
- Issue date Jun 9, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Richard K. Eguchi
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory cell array for improved data retention and meth...
- Patent number 7,259,999
- Issue date Aug 21, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Ronald J. Syzdek
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SECTOR RETIREMENT FOR SPLIT-GATE MEMORY
- Publication number 20170263324
- Publication date Sep 14, 2017
- FREESCALE SEMICONDUCTOR, INC.
- GILLES MULLER
- G11 - INFORMATION STORAGE
Information Patent Application
COMMON SOURCE ARCHITECTURE FOR SPLIT GATE MEMORY
- Publication number 20160314846
- Publication date Oct 27, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Gilles J. MULLER
- G11 - INFORMATION STORAGE
Information Patent Application
SECTOR-BASED REGULATION OF PROGRAM VOLTAGES FOR NON-VOLATILE MEMORY...
- Publication number 20150103602
- Publication date Apr 16, 2015
- Jeffrey C. Cunningham
- G11 - INFORMATION STORAGE
Information Patent Application
SCALABLE SPLIT GATE MEMORY CELL ARRAY
- Publication number 20140319593
- Publication date Oct 30, 2014
- Jane A. YATER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BIASING SPLIT GATE MEMORY CELL DURING POWER-OFF MODE
- Publication number 20140321213
- Publication date Oct 30, 2014
- CHEONG MIN HONG
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING A SPLIT GATE BIT CELL
- Publication number 20140211559
- Publication date Jul 31, 2014
- Cheong M. Hong
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROL GATE WORD LINE DRIVER CIRCUIT FOR MULTIGATE MEMORY
- Publication number 20140119132
- Publication date May 1, 2014
- GILLES MULLER
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURABLE MULTISTAGE CHARGE PUMP USING A SUPPLY DETECT SCHEME
- Publication number 20140022005
- Publication date Jan 23, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Karthik Ramanan
- G11 - INFORMATION STORAGE
Information Patent Application
EMULATED ELECTRICALLY ERASABLE MEMORY HAVING AN ADDRESS RAM FOR DAT...
- Publication number 20130346680
- Publication date Dec 26, 2013
- Ross S. Scouller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SMART CHARGE PUMP CONFIGURATION FOR NON-VOLATILE MEMORIES
- Publication number 20130265828
- Publication date Oct 10, 2013
- Jeffrey C. Cunningham
- G11 - INFORMATION STORAGE
Information Patent Application
READ CONDITIONS FOR A NON-VOLATILE MEMORY (NVM)
- Publication number 20120176844
- Publication date Jul 12, 2012
- Jeffrey C. Cunningham
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR ELECTRICALLY TRIMMING AN NVM REFERENCE CELL
- Publication number 20090296464
- Publication date Dec 3, 2009
- Horacio P. Gasquet
- G11 - INFORMATION STORAGE
Information Patent Application
READ REFERENCE TECHNIQUE WITH CURRENT DEGRADATION PROTECTION
- Publication number 20090231925
- Publication date Sep 17, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Fuchen Mu
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY WITH REDUCED CHARGE FLUENCE
- Publication number 20090180334
- Publication date Jul 16, 2009
- RONALD J. SYZDEK
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTRICAL ERASABLE PROGRAMMABLE MEMORY TRANSCONDUCTANCE TESTING
- Publication number 20090168541
- Publication date Jul 2, 2009
- Richard K. Eguchi
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY ARRAY AND METHODS...
- Publication number 20080247255
- Publication date Oct 9, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Ronald J. Syzdek
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH RETAINED INDICATOR OF READ REFERENCE LEVEL
- Publication number 20080117685
- Publication date May 22, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Ronald J. Syzdek
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH ADJUSTABLE READ REFERENCE BASED ON ECC AND METHO...
- Publication number 20080120526
- Publication date May 22, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Richard K. Eguchi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMING A MEMORY DEVICE HAVING ERROR CORRECTION LOGIC
- Publication number 20080072117
- Publication date Mar 20, 2008
- Ronald J. Syzdek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bit cell reference device and methods thereof
- Publication number 20080043525
- Publication date Feb 21, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Ronald J. Syzdek
- G11 - INFORMATION STORAGE
Information Patent Application
Non-volatile memory cell array for improved data retention and meth...
- Publication number 20070091690
- Publication date Apr 26, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Ronald J. Syzdek
- G11 - INFORMATION STORAGE

Ronald J. Syzdek

Person

Patents Grantslast 30 patents

Scalable split gate memory cell array

Common source architecture for split gate memory

Multibit sense amplifier calibration

Smart charge pump configuration for non-volatile memories

Biasing split gate memory cell during power-off mode

Sector-based regulation of program voltages for non-volatile memory...

Control gate word line driver circuit for multigate memory

Programming a split gate bit cell

Configurable multistage charge pump using a supply detect scheme

Read conditions for a non-volatile memory (NVM)

Memory device with adjustable read reference based on ECC and metho...

Non-volatile memory with reduced charge fluence

Method for electrically trimming an NVM reference cell

Read reference technique with current degradation protection

Electronic device including a nonvolatile memory array and methods...

Bit cell reference device and methods thereof

Programming a memory device having error correction logic

Memory device with retained indicator of read reference level

Electrical erasable programmable memory transconductance testing

Non-volatile memory cell array for improved data retention and meth...

Patents Applicationslast 30 patents

SECTOR RETIREMENT FOR SPLIT-GATE MEMORY

COMMON SOURCE ARCHITECTURE FOR SPLIT GATE MEMORY

SECTOR-BASED REGULATION OF PROGRAM VOLTAGES FOR NON-VOLATILE MEMORY...

SCALABLE SPLIT GATE MEMORY CELL ARRAY

BIASING SPLIT GATE MEMORY CELL DURING POWER-OFF MODE

PROGRAMMING A SPLIT GATE BIT CELL

CONTROL GATE WORD LINE DRIVER CIRCUIT FOR MULTIGATE MEMORY

CONFIGURABLE MULTISTAGE CHARGE PUMP USING A SUPPLY DETECT SCHEME

EMULATED ELECTRICALLY ERASABLE MEMORY HAVING AN ADDRESS RAM FOR DAT...

SMART CHARGE PUMP CONFIGURATION FOR NON-VOLATILE MEMORIES

READ CONDITIONS FOR A NON-VOLATILE MEMORY (NVM)

METHOD FOR ELECTRICALLY TRIMMING AN NVM REFERENCE CELL

READ REFERENCE TECHNIQUE WITH CURRENT DEGRADATION PROTECTION

NON-VOLATILE MEMORY WITH REDUCED CHARGE FLUENCE

ELECTRICAL ERASABLE PROGRAMMABLE MEMORY TRANSCONDUCTANCE TESTING

ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY ARRAY AND METHODS...

MEMORY DEVICE WITH RETAINED INDICATOR OF READ REFERENCE LEVEL

MEMORY DEVICE WITH ADJUSTABLE READ REFERENCE BASED ON ECC AND METHO...

PROGRAMMING A MEMORY DEVICE HAVING ERROR CORRECTION LOGIC

Bit cell reference device and methods thereof

Non-volatile memory cell array for improved data retention and meth...