Ross Segelken

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Instruction-optimizing processor with branch-count table in hardware
- Patent number 10,241,810
- Issue date Mar 26, 2019
- NVIDIA Corporation
- Rupert Brauch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Translation address cache for a microprocessor
- Patent number 10,146,545
- Issue date Dec 4, 2018
- NVIDIA Corporation
- Ross Segelken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Profiling code portions to generate translations
- Patent number 10,108,424
- Issue date Oct 23, 2018
- NVIDIA Corporation
- Nathan Tuck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lazy runahead operation for a microprocessor
- Patent number 9,891,972
- Issue date Feb 13, 2018
- NVIDIA Corporation
- Magnus Ekman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Improving hit rate of code translation redirection table with repla...
- Patent number 9,880,846
- Issue date Jan 30, 2018
- NVIDIA Corporation
- Nathan Tuck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Checkpointed buffer for re-entry from runahead
- Patent number 9,875,105
- Issue date Jan 23, 2018
- NVIDIA Corporation
- Guillermo J. Rozas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Queued instruction re-dispatch after runahead
- Patent number 9,823,931
- Issue date Nov 21, 2017
- NVIDIA Corporation
- Guillermo J. Rozas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing potentially invalid results during runahead
- Patent number 9,740,553
- Issue date Aug 22, 2017
- NVIDIA Corporation
- Bruce Holmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lazy runahead operation for a microprocessor
- Patent number 9,632,976
- Issue date Apr 25, 2017
- NVIDIA Corporation
- Guillermo J. Rozas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic configuration of processing pipeline based on determined ty...
- Patent number 9,563,432
- Issue date Feb 7, 2017
- NVIDIA Corporation
- Ross Segelken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Branch prediction power reduction
- Patent number 9,552,032
- Issue date Jan 24, 2017
- NVIDIA Corporation
- Aneesh Aggarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Branch prediction power reduction
- Patent number 9,547,358
- Issue date Jan 17, 2017
- NVIDIA Corporation
- Aneesh Aggarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction cache power reduction
- Patent number 9,396,117
- Issue date Jul 19, 2016
- NVIDIA Corporation
- Aneesh Aggarwal
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and apparatus for integrated mixed-signal or analog testing
- Patent number 7,262,621
- Issue date Aug 28, 2007
- Synopsys, Inc.
- Aaron Joseph Caffee
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus to execute an instruction with a semi-fast ope...
- Patent number 7,047,397
- Issue date May 16, 2006
- Intel Corporation
- Ross A. Segelken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for address calculation
- Patent number 6,735,682
- Issue date May 11, 2004
- Intel Corporation
- Ross A. Segelken
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LAZY RUNAHEAD OPERATION FOR A MICROPROCESSOR
- Publication number 20170199778
- Publication date Jul 13, 2017
- Magnus Ekman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC CONFIGURATION OF PROCESSING PIPELINE BASED ON DETERMINED TY...
- Publication number 20140317382
- Publication date Oct 23, 2014
- NVIDIA Corporation
- Ross Segelken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROFILING CODE PORTIONS TO GENERATE TRANSLATIONS
- Publication number 20140281392
- Publication date Sep 18, 2014
- NVIDIA Corporation
- Nathan Tuck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAULT DETECTION IN INSTRUCTION TRANSLATIONS
- Publication number 20140189310
- Publication date Jul 3, 2014
- NVIDIA Corporation
- Nathan Tuck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUEUED INSTRUCTION RE-DISPATCH AFTER RUNAHEAD
- Publication number 20140189313
- Publication date Jul 3, 2014
- NVIDIA Corporation
- Guillermo J. Rozas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION CATEGORIZATION FOR RUNAHEAD OPERATION
- Publication number 20140164738
- Publication date Jun 12, 2014
- NVIDIA Corporation
- Magnus Ekman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAZY RUNAHEAD OPERATION FOR A MICROPROCESSOR
- Publication number 20140164736
- Publication date Jun 12, 2014
- NVIDIA Corporation
- Guillermo J. Rozas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING POTENTIALLY INVALID RESULTS DURING RUNAHEAD
- Publication number 20140136891
- Publication date May 15, 2014
- NVIDIA CORPORATION
- Bruce Holmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION-OPTIMIZING PROCESSOR WITH BRANCH-COUNT TABLE IN HARDWARE
- Publication number 20130311752
- Publication date Nov 21, 2013
- NVIDIA Corporation
- Rupert Brauch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHECKPOINTED BUFFER FOR RE-ENTRY FROM RUNAHEAD
- Publication number 20130297911
- Publication date Nov 7, 2013
- NVIDIA Corporation
- Guillermo J. Rozas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BRANCH PREDICTION POWER REDUCTION
- Publication number 20130290640
- Publication date Oct 31, 2013
- NVIDIA Corporation
- Aneesh Aggarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BRANCH PREDICTION POWER REDUCTION
- Publication number 20130290676
- Publication date Oct 31, 2013
- NVIDIA Corporation
- Aneesh Aggarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCESSING AND MANAGING CODE TRANSLATIONS IN A MICROPROCESSOR
- Publication number 20130275684
- Publication date Oct 17, 2013
- NVIDIA Corporation
- Nathan Tuck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSLATION ADDRESS CACHE FOR A MICROPROCESSOR
- Publication number 20130246709
- Publication date Sep 19, 2013
- NVIDIA Corporation
- Ross Segelken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION CACHE POWER REDUCTION
- Publication number 20130179640
- Publication date Jul 11, 2013
- NVIDIA Corporation
- Aneesh Aggarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to execute an instruction with a semi-fast ope...
- Publication number 20060206693
- Publication date Sep 14, 2006
- Ross A. Segelken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for variable length instruction parallel decoding
- Publication number 20040128479
- Publication date Jul 1, 2004
- Venkateswara Rao Madduri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to execute an instruction with a semi-fast ope...
- Publication number 20040054875
- Publication date Mar 18, 2004
- Ross A. Segelken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for address calculation
- Publication number 20030188125
- Publication date Oct 2, 2003
- Ross A. Segelken
- G06 - COMPUTING CALCULATING COUNTING

Ross Segelken

Person

Patents Grantslast 30 patents

Instruction-optimizing processor with branch-count table in hardware

Translation address cache for a microprocessor

Profiling code portions to generate translations

Lazy runahead operation for a microprocessor

Improving hit rate of code translation redirection table with repla...

Checkpointed buffer for re-entry from runahead

Queued instruction re-dispatch after runahead

Managing potentially invalid results during runahead

Lazy runahead operation for a microprocessor

Dynamic configuration of processing pipeline based on determined ty...

Branch prediction power reduction

Branch prediction power reduction

Instruction cache power reduction

Method and apparatus for integrated mixed-signal or analog testing

Method and apparatus to execute an instruction with a semi-fast ope...

Apparatus and method for address calculation

Patents Applicationslast 30 patents

LAZY RUNAHEAD OPERATION FOR A MICROPROCESSOR

DYNAMIC CONFIGURATION OF PROCESSING PIPELINE BASED ON DETERMINED TY...

PROFILING CODE PORTIONS TO GENERATE TRANSLATIONS

FAULT DETECTION IN INSTRUCTION TRANSLATIONS

QUEUED INSTRUCTION RE-DISPATCH AFTER RUNAHEAD

INSTRUCTION CATEGORIZATION FOR RUNAHEAD OPERATION

LAZY RUNAHEAD OPERATION FOR A MICROPROCESSOR

MANAGING POTENTIALLY INVALID RESULTS DURING RUNAHEAD

INSTRUCTION-OPTIMIZING PROCESSOR WITH BRANCH-COUNT TABLE IN HARDWARE

CHECKPOINTED BUFFER FOR RE-ENTRY FROM RUNAHEAD

BRANCH PREDICTION POWER REDUCTION

BRANCH PREDICTION POWER REDUCTION

ACCESSING AND MANAGING CODE TRANSLATIONS IN A MICROPROCESSOR

TRANSLATION ADDRESS CACHE FOR A MICROPROCESSOR

INSTRUCTION CACHE POWER REDUCTION

Method and apparatus to execute an instruction with a semi-fast ope...

Method and apparatus for variable length instruction parallel decoding

Method and apparatus to execute an instruction with a semi-fast ope...

Apparatus and method for address calculation