Sabyasachi Das

Follow

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Synthesis of fast squarer functional blocks
- Patent number 9,043,735
- Issue date May 26, 2015
- Cadence Design Systems, Inc.
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synthesis of area-efficient subtractor and divider functional blocks
- Patent number 8,707,225
- Issue date Apr 22, 2014
- Cadence Design Systems, Inc.
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Full subtractor cell for synthesis of area-efficient subtractor and...
- Patent number 8,407,277
- Issue date Mar 26, 2013
- Cadence Design Systems, Inc.
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing driven synthesis of sum-of-product functional blocks
- Patent number 7,739,324
- Issue date Jun 15, 2010
- Cadence Design Systems, Inc.
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Datapath design methodology and routing apparatus
- Patent number 6,598,215
- Issue date Jul 22, 2003
- Intel Corporation
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Datapath design methodology and routing apparatus
- Publication number 20020144227
- Publication date Oct 3, 2002
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING