Sam Sivakumar

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Non-planar transistors with channel regions having varying widths
- Patent number 11,569,231
- Issue date Jan 31, 2023
- Intel Corporation
- Stephen D Snyder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Diagonal corner-to-corner sub-resolution assist features for photol...
- Patent number 7,648,803
- Issue date Jan 19, 2010
- Intel Corporation
- Sam Sivakumar
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Methods to pattern contacts using chromeless phase shift masks
- Patent number 7,374,865
- Issue date May 20, 2008
- Intel Corporation
- Paul Nyhus
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Chromeless phase shift lithography (CPL) masks having features to p...
- Patent number 7,179,570
- Issue date Feb 20, 2007
- Intel Corporation
- Sam Sivakumar
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Use of chromeless phase shift features to pattern large area line/s...
- Patent number 7,056,645
- Issue date Jun 6, 2006
- Intel Corporation
- Sam Sivakumar
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method integrating polymeric interlayer dielectric in integrated ci...
- Patent number 6,774,037
- Issue date Aug 10, 2004
- Intel Corporation
- Makarem A. Hussein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Photoimageable material patterning techniques useful in fabricating...
- Patent number 6,649,515
- Issue date Nov 18, 2003
- Intel Corporation
- Peter K. Moon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pattern-sensitive deposition for damascene processing
- Patent number 6,406,995
- Issue date Jun 18, 2002
- Intel Corporation
- Makarem A. Hussein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single step electroplating process for interconnect via fill and me...
- Patent number 6,384,481
- Issue date May 7, 2002
- Intel Corporation
- Makarem Hussein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for patterning dual damascene interconnects using a sacrific...
- Patent number 6,365,529
- Issue date Apr 2, 2002
- Intel Corporation
- Makarem A. Hussein
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method for making a semiconductor device having a carbon doped oxid...
- Patent number 6,350,670
- Issue date Feb 26, 2002
- Intel Corporation
- Ebrahim Andideh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for patterning dual damascene interconnects using a sacrific...
- Patent number 6,329,118
- Issue date Dec 11, 2001
- Intel Corporation
- Makarem A. Hussein
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method for making integrated circuit having polymer interlayer diel...
- Patent number 6,037,255
- Issue date Mar 14, 2000
- Intel Corporation
- Makarem A. Hussein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single step electroplating process for interconnect via fill and me...
- Patent number 6,020,266
- Issue date Feb 1, 2000
- Intel Corporation
- Makarem Hussein
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
NON-PLANAR TRANSISTORS WITH CHANNEL REGIONS HAVING VARYING WIDTHS
- Publication number 20200295002
- Publication date Sep 17, 2020
- Intel Corporation
- Stephen D. Snyder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Diagonal corner-to-corner sub-resolution assist features for photol...
- Publication number 20070224519
- Publication date Sep 27, 2007
- Intel Corporation
- Sam Sivakumar
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Use of chromeless phase shift features to pattern large area line/s...
- Publication number 20060083998
- Publication date Apr 20, 2006
- Sam Sivakumar
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Use of chromeless phase shift features to pattern large area line/s...
- Publication number 20040101765
- Publication date May 27, 2004
- Sam Sivakumar
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method integrating polymeric interlayer dielectric in integrated ci...
- Publication number 20030216057
- Publication date Nov 20, 2003
- Makarem A. Hussein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PATTERNING DUAL DAMASCENE INTERCONNECTS USING A SACRIFIC...
- Publication number 20010055725
- Publication date Dec 27, 2001
- MAKAREM A. HUSSEIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PATTERNING CONDUCTIVE LINES IN CIRCUIT STRUCTURES
- Publication number 20010021581
- Publication date Sep 13, 2001
- PETER K MOON
- H01 - BASIC ELECTRIC ELEMENTS

Sam Sivakumar

Person

Patents Grantslast 30 patents

Non-planar transistors with channel regions having varying widths

Diagonal corner-to-corner sub-resolution assist features for photol...

Methods to pattern contacts using chromeless phase shift masks

Chromeless phase shift lithography (CPL) masks having features to p...

Use of chromeless phase shift features to pattern large area line/s...

Method integrating polymeric interlayer dielectric in integrated ci...

Photoimageable material patterning techniques useful in fabricating...

Pattern-sensitive deposition for damascene processing

Single step electroplating process for interconnect via fill and me...

Method for patterning dual damascene interconnects using a sacrific...

Method for making a semiconductor device having a carbon doped oxid...

Method for patterning dual damascene interconnects using a sacrific...

Method for making integrated circuit having polymer interlayer diel...

Single step electroplating process for interconnect via fill and me...

Patents Applicationslast 30 patents

NON-PLANAR TRANSISTORS WITH CHANNEL REGIONS HAVING VARYING WIDTHS

Diagonal corner-to-corner sub-resolution assist features for photol...

Use of chromeless phase shift features to pattern large area line/s...

Use of chromeless phase shift features to pattern large area line/s...

Method integrating polymeric interlayer dielectric in integrated ci...

METHOD FOR PATTERNING DUAL DAMASCENE INTERCONNECTS USING A SACRIFIC...

PATTERNING CONDUCTIVE LINES IN CIRCUIT STRUCTURES