Sandeep Brahmadathan

Person

Dublin, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Parity protected memory blocks merged with error correction code (E...
- Patent number 12,314,130
- Issue date May 27, 2025
- Ampere Computing LLC
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Component die validation built-in self-test (VBIST) engine
- Patent number 12,282,064
- Issue date Apr 22, 2025
- Ampere Computing LLC
- Sandeep Brahmadathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated error correction code (ECC) and parity protection in mem...
- Patent number 12,204,410
- Issue date Jan 21, 2025
- Ampere Computing LLC
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extending functionality of memory controllers in a processor-based...
- Patent number 12,159,056
- Issue date Dec 3, 2024
- Ampere Computing LLC
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Advanced initialization bus (AIB)
- Patent number 12,019,565
- Issue date Jun 25, 2024
- Ampere Computing LLC
- Sandeep Brahmadathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parity protected memory blocks merged with error correction code (E...
- Patent number 11,934,263
- Issue date Mar 19, 2024
- Ampere Computing LLC
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for sequencing data checks in a packet
- Patent number 11,868,209
- Issue date Jan 9, 2024
- Ampere Computing LLC
- Matthew Robert Erler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for sequencing data checks in a packet
- Patent number 11,481,270
- Issue date Oct 25, 2022
- Ampere Computing LLC
- Matthew Robert Erler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory data transfer and switching sequence
- Patent number 10,885,952
- Issue date Jan 5, 2021
- Cadence Design Systems, Inc.
- Sandeep Brahmadathan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
COMPONENT DIE VALIDATION BUILT-IN SELF-TEST (VBIST) ENGINE
- Publication number 20250231236
- Publication date Jul 17, 2025
- Ampere Computing LLC
- Sandeep BRAHMADATHAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTENDING FUNCTIONALITY OF MEMORY CONTROLLERS USING A LOOPBACK MODE...
- Publication number 20250131970
- Publication date Apr 24, 2025
- Ampere Computing LLC
- Massimo Sutera
- G11 - INFORMATION STORAGE
Information Patent Application
ADVANCED INITIALIZATION BUS (AIB)
- Publication number 20240320165
- Publication date Sep 26, 2024
- Ampere Computing LLC
- Sandeep BRAHMADATHAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARITY PROTECTED MEMORY BLOCKS MERGED WITH ERROR CORRECTION CODE (E...
- Publication number 20240220356
- Publication date Jul 4, 2024
- Ampere Computing LLC
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTENDING FUNCTIONALITY OF MEMORY CONTROLLERS IN A PROCESSOR-BASED...
- Publication number 20240004577
- Publication date Jan 4, 2024
- Ampere Computing LLC
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADVANCED INITIALIZATION BUS (AIB)
- Publication number 20240004806
- Publication date Jan 4, 2024
- Ampere Computing LLC
- Sandeep BRAHMADATHAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPONENT DIE VALIDATION BUILT-IN SELF-TEST (VBIST) ENGINE
- Publication number 20240003974
- Publication date Jan 4, 2024
- Ampere Computing LLC
- Sandeep BRAHMADATHAN
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED ERROR CORRECTION CODE (ECC) AND PARITY PROTECTION IN MEM...
- Publication number 20230315571
- Publication date Oct 5, 2023
- Ampere Computing LLC
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARITY PROTECTED MEMORY BLOCKS MERGED WITH ERROR CORRECTION CODE (E...
- Publication number 20230315565
- Publication date Oct 5, 2023
- Ampere Computing LLC
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR SEQUENCING DATA CHECKS IN A PACKET
- Publication number 20230058854
- Publication date Feb 23, 2023
- Ampere Computing LLC
- Matthew Robert ERLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES, SYSTEMS, AND METHODS FOR IMPLIED SEQUENCE NUMBERING OF...
- Publication number 20220407813
- Publication date Dec 22, 2022
- Ampere Computing LLC
- Matthew Robert Erler
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND SYSTEM FOR DATA TRANSACTIONS ON A COMMUNICATIONS INTERFACE
- Publication number 20220405223
- Publication date Dec 22, 2022
- Ampere Computing LLC
- Matthew Robert ERLER
- G06 - COMPUTING CALCULATING COUNTING

Sandeep Brahmadathan

Person

Patents Grantslast 30 patents

Parity protected memory blocks merged with error correction code (E...

Component die validation built-in self-test (VBIST) engine

Integrated error correction code (ECC) and parity protection in mem...

Extending functionality of memory controllers in a processor-based...

Advanced initialization bus (AIB)

Parity protected memory blocks merged with error correction code (E...

Method and system for sequencing data checks in a packet

Method and system for sequencing data checks in a packet

Memory data transfer and switching sequence

Patents Applicationslast 30 patents

COMPONENT DIE VALIDATION BUILT-IN SELF-TEST (VBIST) ENGINE

EXTENDING FUNCTIONALITY OF MEMORY CONTROLLERS USING A LOOPBACK MODE...

ADVANCED INITIALIZATION BUS (AIB)

PARITY PROTECTED MEMORY BLOCKS MERGED WITH ERROR CORRECTION CODE (E...

EXTENDING FUNCTIONALITY OF MEMORY CONTROLLERS IN A PROCESSOR-BASED...

ADVANCED INITIALIZATION BUS (AIB)

COMPONENT DIE VALIDATION BUILT-IN SELF-TEST (VBIST) ENGINE

INTEGRATED ERROR CORRECTION CODE (ECC) AND PARITY PROTECTION IN MEM...

PARITY PROTECTED MEMORY BLOCKS MERGED WITH ERROR CORRECTION CODE (E...

METHOD AND SYSTEM FOR SEQUENCING DATA CHECKS IN A PACKET

APPARATUSES, SYSTEMS, AND METHODS FOR IMPLIED SEQUENCE NUMBERING OF...

METHOD AND SYSTEM FOR DATA TRANSACTIONS ON A COMMUNICATIONS INTERFACE