Sang Hoo Dhong

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamic random access memory (DRAM) cells and methods for fabricati...
- Patent number 8,618,592
- Issue date Dec 31, 2013
- Advanced Micro Devices, Inc.
- Hyun-Jin Cho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device and method thereof
- Patent number 8,464,130
- Issue date Jun 11, 2013
- GlobalFoundries Inc.
- Sang Dhong
- G11 - INFORMATION STORAGE
Information Patent Grant
Reducing power requirements of a multiple core processor
- Patent number 8,381,006
- Issue date Feb 19, 2013
- International Business Machines Corporation
- Brian K. Flachs
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method for controlling rounding modes in single instruction multipl...
- Patent number 8,229,989
- Issue date Jul 24, 2012
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing the latency of sum-addressed shifters
- Patent number 8,166,085
- Issue date Apr 24, 2012
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of logic circuit synthesis and design using a dynamic circui...
- Patent number 8,136,061
- Issue date Mar 13, 2012
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed adder design for a multiply-add based floating point unit
- Patent number 8,131,795
- Issue date Mar 6, 2012
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
LSSD compatibility for GSD unified global clock buffers
- Patent number 8,117,579
- Issue date Feb 14, 2012
- International Business Machines Corporation
- James Douglas Warnock
- G01 - MEASURING TESTING
Information Patent Grant
Dynamic random access memory (DRAM) cells and methods for fabricati...
- Patent number 7,977,172
- Issue date Jul 12, 2011
- Advanced Micro Devices, Inc.
- Hyun-Jin Cho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Scan chain disable function for power saving
- Patent number 7,962,811
- Issue date Jun 14, 2011
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating a worst case current waveform for testing of integrated...
- Patent number 7,917,347
- Issue date Mar 29, 2011
- International Business Machines Corporation
- Makoto Aikawa
- G01 - MEASURING TESTING
Information Patent Grant
Scannable latch
- Patent number 7,746,140
- Issue date Jun 29, 2010
- International Business Machines Corporation
- Sang Hoo Dhong
- G01 - MEASURING TESTING
Information Patent Grant
Voltage identifier sorting
- Patent number 7,739,573
- Issue date Jun 15, 2010
- International Business Machines Corporation
- Jonathan J. DeMent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device and method of refreshing
- Patent number 7,724,567
- Issue date May 25, 2010
- Advanced Micro Devices, Inc.
- Sang Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for controlling operation of microprocessor which performs d...
- Patent number 7,716,516
- Issue date May 11, 2010
- Sony Computer Entertainment Inc.
- Yosuke Muraki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Level shifter for boosting wordline voltage and memory cell perform...
- Patent number 7,710,796
- Issue date May 4, 2010
- International Business Machines Corporation
- Scott R. Cottier
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with combined line and word access
- Patent number 7,617,338
- Issue date Nov 10, 2009
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modifying a test pattern to control power supply noise
- Patent number 7,610,531
- Issue date Oct 27, 2009
- International Business Machines Corporation
- Sang H. Dhong
- G01 - MEASURING TESTING
Information Patent Grant
Random carry-in for floating-point operations
- Patent number 7,493,357
- Issue date Feb 17, 2009
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed adder design for a multiply-add based floating point unit
- Patent number 7,490,119
- Issue date Feb 10, 2009
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for testing to determine minimum operating vol...
- Patent number 7,486,096
- Issue date Feb 3, 2009
- International Business Machines Corporation
- Sang H. Dhong
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatus for performing multi-value range checks
- Patent number 7,469,265
- Issue date Dec 23, 2008
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for controlling rounding modes in single instruction mult...
- Patent number 7,447,725
- Issue date Nov 4, 2008
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for sorting processors based on thermal design point
- Patent number 7,447,602
- Issue date Nov 4, 2008
- International Business Machines Corporation
- Douglas H. Bradley
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatus for reducing leakage current in a disabled SO...
- Patent number 7,444,525
- Issue date Oct 28, 2008
- Sony Computer Entertainment Inc.
- Hiroshi Yoshihara
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for wordline redundancy control of memory in a...
- Patent number 7,423,921
- Issue date Sep 9, 2008
- International Business Machines Corporation
- Toru Asano
- G11 - INFORMATION STORAGE
Information Patent Grant
Processor having efficient function estimate instructions
- Patent number 7,406,589
- Issue date Jul 29, 2008
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for reducing the latency of sum-addressed shif...
- Patent number 7,392,270
- Issue date Jun 24, 2008
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of logic circuit synthesis and design using a dynamic circui...
- Patent number 7,363,609
- Issue date Apr 22, 2008
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory array manufacturing defect detection system and method
- Patent number 7,318,182
- Issue date Jan 8, 2008
- International Business Machines Corporation
- Louis Bernard Bushard
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Reducing Power Requirements of a Multiple Core Processor
- Publication number 20110252260
- Publication date Oct 13, 2011
- International Business Machines Corporation
- Brian K. Flachs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS AND METHODS FOR FABRICATI...
- Publication number 20110204429
- Publication date Aug 25, 2011
- Advanced Micro Devices, Inc.
- Hyun-Jin CHO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS AND METHODS FOR FABRICATI...
- Publication number 20100144106
- Publication date Jun 10, 2010
- Advanced Micro Devices, Inc.
- Hyun-Jin CHO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICE AND METHOD THEREOF
- Publication number 20100146330
- Publication date Jun 10, 2010
- Advanced Micro check here
- Sang Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SENSE AMPLIFIER BASED FLIP-FLOP
- Publication number 20100102867
- Publication date Apr 29, 2010
- Sang H. Dhong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY DEVICE AND METHOD
- Publication number 20100002482
- Publication date Jan 7, 2010
- Advanced Micro Devices, Inc.
- Sang Dhong
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND METHOD OF REFRESHING
- Publication number 20100002502
- Publication date Jan 7, 2010
- Advanced Micro Devices, Inc.
- Sang Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LSSD compatibility for GSD unified global clock buffers
- Publication number 20090199036
- Publication date Aug 6, 2009
- James D. Warnock
- G01 - MEASURING TESTING
Information Patent Application
Maintaining Circuit Delay Characteristics During Power Management Mode
- Publication number 20090121747
- Publication date May 14, 2009
- Sang Hoo Dhong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LEVEL SHIFTER FOR BOOSTING WORDLINE VOLTAGE AND MEMORY CELL PERFORM...
- Publication number 20090116307
- Publication date May 7, 2009
- Scott R. Cottier
- G11 - INFORMATION STORAGE
Information Patent Application
System and Method for Generating a Worst Case Current Waveform for...
- Publication number 20090112550
- Publication date Apr 30, 2009
- Makoto Aikawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH SPEED ADDER DESIGN FOR A MULTIPLY-ADD BASED FLOATING POINT UNIT
- Publication number 20090077155
- Publication date Mar 19, 2009
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Controlling Rounding Modes in Single Instruction Multi...
- Publication number 20090024684
- Publication date Jan 22, 2009
- IBM Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor Having Efficient Function Estimate Instructions
- Publication number 20080263336
- Publication date Oct 23, 2008
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus for Reducing the Latency of Sum-Addressed Shifters
- Publication number 20080195684
- Publication date Aug 14, 2008
- International Business Machines Corporation
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF LOGIC CIRCUIT SYNTHESIS AND DESIGN USING A DYNAMIC CIRCUI...
- Publication number 20080189670
- Publication date Aug 7, 2008
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Determining a Guard Band for an Operating Vol...
- Publication number 20080189090
- Publication date Aug 7, 2008
- Makoto Aikawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Voltage Identifier Sorting
- Publication number 20080168318
- Publication date Jul 10, 2008
- Jonathan J. DeMent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Testing to Determine Minimum Operating Vol...
- Publication number 20080100328
- Publication date May 1, 2008
- IBM Corporation
- Sang H. Dhong
- G01 - MEASURING TESTING
Information Patent Application
Optimizing a Set of LBIST Patterns to Enhance Delay Fault Coverage
- Publication number 20080092006
- Publication date Apr 17, 2008
- Nikhil Dakwala
- G01 - MEASURING TESTING
Information Patent Application
System and Method for Modifying a Test Pattern to Control Power Su...
- Publication number 20080082887
- Publication date Apr 3, 2008
- Sang H. Dhong
- G01 - MEASURING TESTING
Information Patent Application
METHOD FOR PERFORMING POWER SIMULATIONS ON COMPLEX DESIGNS RUNNING...
- Publication number 20080021692
- Publication date Jan 24, 2008
- Rajat Chaudhry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Wordline Redundancy Control of Memory in a...
- Publication number 20080013388
- Publication date Jan 17, 2008
- IBM Corporation
- Toru Asano
- G11 - INFORMATION STORAGE
Information Patent Application
Method for controlling operation of microprocessor which performs d...
- Publication number 20070300082
- Publication date Dec 27, 2007
- Sony Computer Entertainment Inc.
- Yosuke Muraki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scannable Latch
- Publication number 20070079193
- Publication date Apr 5, 2007
- Sang Hoo Dhong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Scan Chain Disable Function for Power Saving
- Publication number 20070061647
- Publication date Mar 15, 2007
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Byte Execution Unit for Carrying Out Byte Instructions in a Processor
- Publication number 20070061553
- Publication date Mar 15, 2007
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for row based power control of a microprocesso...
- Publication number 20070043895
- Publication date Feb 22, 2007
- Chad Allen Adams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for reducing leakage current in a disabled SO...
- Publication number 20060270173
- Publication date Nov 30, 2006
- SCEI Inc.
- Hiroshi Yoshihara
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Processor having efficient function estimate instructions
- Publication number 20060259745
- Publication date Nov 16, 2006
- Sang Hoo Dhong
- G06 - COMPUTING CALCULATING COUNTING

Sang Hoo Dhong

Person

Patents Grantslast 30 patents

Dynamic random access memory (DRAM) cells and methods for fabricati...

Memory device and method thereof

Reducing power requirements of a multiple core processor

Method for controlling rounding modes in single instruction multipl...

Reducing the latency of sum-addressed shifters

Method of logic circuit synthesis and design using a dynamic circui...

High speed adder design for a multiply-add based floating point unit

LSSD compatibility for GSD unified global clock buffers

Dynamic random access memory (DRAM) cells and methods for fabricati...

Scan chain disable function for power saving

Generating a worst case current waveform for testing of integrated...

Scannable latch

Voltage identifier sorting

Memory device and method of refreshing

Method for controlling operation of microprocessor which performs d...

Level shifter for boosting wordline voltage and memory cell perform...

Memory with combined line and word access

Modifying a test pattern to control power supply noise

Random carry-in for floating-point operations

High speed adder design for a multiply-add based floating point unit

Method and apparatus for testing to determine minimum operating vol...

Methods and apparatus for performing multi-value range checks

Apparatus for controlling rounding modes in single instruction mult...

System and method for sorting processors based on thermal design point

Methods and apparatus for reducing leakage current in a disabled SO...

Method and apparatus for wordline redundancy control of memory in a...

Processor having efficient function estimate instructions

Apparatus and method for reducing the latency of sum-addressed shif...

Method of logic circuit synthesis and design using a dynamic circui...

Memory array manufacturing defect detection system and method

Patents Applicationslast 30 patents

Reducing Power Requirements of a Multiple Core Processor

DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS AND METHODS FOR FABRICATI...

DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS AND METHODS FOR FABRICATI...

MEMORY DEVICE AND METHOD THEREOF

SENSE AMPLIFIER BASED FLIP-FLOP

MEMORY DEVICE AND METHOD

MEMORY DEVICE AND METHOD OF REFRESHING

LSSD compatibility for GSD unified global clock buffers

Maintaining Circuit Delay Characteristics During Power Management Mode

LEVEL SHIFTER FOR BOOSTING WORDLINE VOLTAGE AND MEMORY CELL PERFORM...

System and Method for Generating a Worst Case Current Waveform for...

HIGH SPEED ADDER DESIGN FOR A MULTIPLY-ADD BASED FLOATING POINT UNIT

Method for Controlling Rounding Modes in Single Instruction Multi...

Processor Having Efficient Function Estimate Instructions

Apparatus for Reducing the Latency of Sum-Addressed Shifters

METHOD OF LOGIC CIRCUIT SYNTHESIS AND DESIGN USING A DYNAMIC CIRCUI...

System and Method for Determining a Guard Band for an Operating Vol...

Voltage Identifier Sorting

Method and Apparatus for Testing to Determine Minimum Operating Vol...

Optimizing a Set of LBIST Patterns to Enhance Delay Fault Coverage

System and Method for Modifying a Test Pattern to Control Power Su...

METHOD FOR PERFORMING POWER SIMULATIONS ON COMPLEX DESIGNS RUNNING...

Method and Apparatus for Wordline Redundancy Control of Memory in a...

Method for controlling operation of microprocessor which performs d...

Scannable Latch

Scan Chain Disable Function for Power Saving

Byte Execution Unit for Carrying Out Byte Instructions in a Processor

Method and apparatus for row based power control of a microprocesso...

Methods and apparatus for reducing leakage current in a disabled SO...

Processor having efficient function estimate instructions