Sang Yee Loong

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Via electromigration improvement by changing the via bottom geometr...
- Patent number 7,781,895
- Issue date Aug 24, 2010
- Chartered Semiconductor Manufacturing Ltd.
- Bei Chao Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via electromigration improvement by changing the via bottom geometr...
- Patent number 7,691,739
- Issue date Apr 6, 2010
- Chartered Semiconductor Manufacturing Ltd.
- Bei Chao Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via electromigration improvement by changing the via bottom geometr...
- Patent number 7,045,455
- Issue date May 16, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Beichao Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of body contact for SOI MOSFET
- Patent number 6,963,113
- Issue date Nov 8, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Ting Cheong Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of body contact for SOI mosfet
- Patent number 6,787,422
- Issue date Sep 7, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Ting Cheong Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a high K metallic dielectric layer
- Patent number 6,764,914
- Issue date Jul 20, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Alex See
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of vacuum packaging a semiconductor device assembly
- Patent number 6,737,739
- Issue date May 18, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Shyue-Fong Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical source/drain contact semiconductor
- Patent number 6,653,674
- Issue date Nov 25, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Shyue Fong Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming PID protection diode for SOI wafer
- Patent number 6,611,024
- Issue date Aug 26, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Ting Cheong Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Simplified method of fabricating a rim phase shift mask
- Patent number 6,582,856
- Issue date Jun 24, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Shyue Fong Quek
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method for selective oxide etching in pre-metal deposition
- Patent number 6,530,380
- Issue date Mar 11, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Mei Sheng Zhou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of vacuum packaging a semiconductor device assembly
- Patent number 6,495,399
- Issue date Dec 17, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Shyue-Fong Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming of high K metallic dielectric layer
- Patent number 6,492,242
- Issue date Dec 10, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Alex See
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip scale packaging with multi-layer flip chip arrangement and bal...
- Patent number 6,492,726
- Issue date Dec 10, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Shyue Fong Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ESD protection network used for SOI technology
- Patent number 6,486,515
- Issue date Nov 26, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Song Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical source/drain contact semiconductor
- Patent number 6,465,296
- Issue date Oct 15, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Shyue Fong Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Alternating phase shift mask and method for fabricating the alignme...
- Patent number 6,416,909
- Issue date Jul 9, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Shyue Fong Quek
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Triple-layered low dielectric constant dielectric dual damascene ap...
- Patent number 6,406,994
- Issue date Jun 18, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Ting Cheong Ang
- B41 - PRINTING LINING MACHINES TYPEWRITERS STAMPS
Information Patent Grant
Method for forming an ESD protection network for SOI technology wit...
- Patent number 6,406,948
- Issue date Jun 18, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Song Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ESD protection device for SOI technology
- Patent number 6,399,431
- Issue date Jun 4, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Jun Song
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of hard mask patterning
- Patent number 6,376,379
- Issue date Apr 23, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Shyue Fong Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming PID protection diode for SOI wafer
- Patent number 6,303,414
- Issue date Oct 16, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Ting Cheong Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of field isolation in silicon-on-insulator technology
- Patent number 6,300,172
- Issue date Oct 9, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Ting Cheong Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to fabricate a MOSFET using selective epitaxial growth to fo...
- Patent number 6,284,609
- Issue date Sep 4, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Ting Cheong Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-K MOM capacitor
- Patent number 6,261,917
- Issue date Jul 17, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Shyue Fong Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form, and structure of, a dual damascene interconnect device
- Patent number 6,252,290
- Issue date Jun 26, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Shyue Fong Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabrication of dual gate oxides for CMOS devices
- Patent number 6,248,618
- Issue date Jun 19, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Shyue Fong Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to fabricate a sub-quarter-micron MOSFET with lightly doped...
- Patent number 6,214,680
- Issue date Apr 10, 2001
- Chartered Semiconductor Manufacturing, Ltd.
- Shyue Fong Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a MOS device
- Patent number 6,110,787
- Issue date Aug 29, 2000
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
VIA ELECTROMIGRATION IMPROVEMENT BY CHANGING THE VIA BOTTOM GEOMETR...
- Publication number 20090250818
- Publication date Oct 8, 2009
- Chartered Semiconductor Manufacturing LTD.
- Bei Chao Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Via electromigration improvement by changing the via bottom geometr...
- Publication number 20060160354
- Publication date Jul 20, 2006
- Chartered Semiconductor Manufacturing LTD.
- BeiChao Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Via electromigration improvement by changing the via bottom geometr...
- Publication number 20050090097
- Publication date Apr 28, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Beichao Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Novel method of body contact for SOI MOSFET
- Publication number 20050014294
- Publication date Jan 20, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Ting Cheong Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming a high K metallic dielectric layer
- Publication number 20030104673
- Publication date Jun 5, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Alex See
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of vacuum packaging a semiconductor device assembly
- Publication number 20030052403
- Publication date Mar 20, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Shyue-Fong Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Vertical source/drain contact semiconductor
- Publication number 20030006462
- Publication date Jan 9, 2003
- Shyue Fong Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL SOURCE/DRAIN CONTACT SEMICONDUCTOR
- Publication number 20020151108
- Publication date Oct 17, 2002
- Shyue Fong Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ESD PROTECTION NETWORK USED FOR SOI TECHNOLOGY
- Publication number 20020115239
- Publication date Aug 22, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Song Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Novel method of body contact for SOI mosfet
- Publication number 20020089031
- Publication date Jul 11, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Ting Cheong Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Vertical source/drain contact semiconductor
- Publication number 20020048884
- Publication date Apr 25, 2002
- Shyue Fong Quek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming PID protection diode for SOI wafer
- Publication number 20020022328
- Publication date Feb 21, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Ting Cheong Ang
- H01 - BASIC ELECTRIC ELEMENTS

Sang Yee Loong

Person

Patents Grantslast 30 patents

Via electromigration improvement by changing the via bottom geometr...

Via electromigration improvement by changing the via bottom geometr...

Via electromigration improvement by changing the via bottom geometr...

Method of body contact for SOI MOSFET

Method of body contact for SOI mosfet

Method of forming a high K metallic dielectric layer

Method of vacuum packaging a semiconductor device assembly

Vertical source/drain contact semiconductor

Method of forming PID protection diode for SOI wafer

Simplified method of fabricating a rim phase shift mask

Method for selective oxide etching in pre-metal deposition

Method of vacuum packaging a semiconductor device assembly

Method of forming of high K metallic dielectric layer

Chip scale packaging with multi-layer flip chip arrangement and bal...

ESD protection network used for SOI technology

Vertical source/drain contact semiconductor

Alternating phase shift mask and method for fabricating the alignme...

Triple-layered low dielectric constant dielectric dual damascene ap...

Method for forming an ESD protection network for SOI technology wit...

ESD protection device for SOI technology

Method of hard mask patterning

Method of forming PID protection diode for SOI wafer

Method of field isolation in silicon-on-insulator technology

Method to fabricate a MOSFET using selective epitaxial growth to fo...

High-K MOM capacitor

Method to form, and structure of, a dual damascene interconnect device

Method of fabrication of dual gate oxides for CMOS devices

Method to fabricate a sub-quarter-micron MOSFET with lightly doped...

Method for fabricating a MOS device

Patents Applicationslast 30 patents

VIA ELECTROMIGRATION IMPROVEMENT BY CHANGING THE VIA BOTTOM GEOMETR...

Via electromigration improvement by changing the via bottom geometr...

Via electromigration improvement by changing the via bottom geometr...

Novel method of body contact for SOI MOSFET

Method of forming a high K metallic dielectric layer

Method of vacuum packaging a semiconductor device assembly

Vertical source/drain contact semiconductor

VERTICAL SOURCE/DRAIN CONTACT SEMICONDUCTOR

ESD PROTECTION NETWORK USED FOR SOI TECHNOLOGY

Novel method of body contact for SOI mosfet

Vertical source/drain contact semiconductor

Method of forming PID protection diode for SOI wafer