Claims
- 1. A semiconductor device comprising:
a semiconductor substrate having a contact trench provided therein; a gate dielectric disposed over the semiconductor substrateadjacent the contact trench; a gate disposed over the gate dielectric; a source/drain junction disposed in the semiconductor substrate adjacent the contact trench; and a conductive contact disposed in the contact trench conductively connected to the source/drain junction, the conductive contact having inwardly curved cross-sectional widths in the semiconductor substrate.
- 2. The semiconductor device as claimed in claim 1 wherein the conductive contact has the inwardly curved cross-sectional widths with a top width and a subsurface width in the semiconductor substrate, the sub-surface width is less than about 50% of the top width.
- 3. The semiconductor device as claimed in claim 1 wherein the conductive contact has the inwardly curved cross-sectional widths with a top width and a subsurface width in the semiconductor substrate, the sub-surface width is between about 50% and about 10% of the top width.
- 4. The semiconductor device as claimed in claim 1 including a dielectric layer over the semiconductor substrate having the conductive contact extending therethrough, the conductive contact having a width in the dielectric layer equal to the top width thereof at the surface of the semiconductor substrate.
- 5. The semiconductor device as claimed in claim 1 wherein the contact trench is lined with a salicide.
- 6. The semiconductor device as claimed in claim 1 wherein the source/drain junction includes an extension source/drain junction having a highest doping concentration below the surface of the semiconductor substrate.
- 7. The semiconductor device as claimed in claim 1 including:
an insulator layer disposed below the semiconductor substrate; and a further semiconductor substrate disposed below the insulator layer.
- 8. The semiconductor device as claimed in claim 1 including an isolation insulator disposed around the source/drain junction and the conductive contact, the isolation insulator disposed in the semiconductor substrate.
- 9. A semiconductor device comprising:
a silicon substrate having first and second contact trenches provided therein; a gate oxide layer disposed over the silicon substratebetween the first and second contact trenches; a polysilicon gate over the gate oxide layer; source/drain junctions disposed adjacent sides of the gate oxide layer in the silicon substrate; and first and second conductive contacts respectively disposed in the first and second contact trenches conductively connected to the source/drain junctions, the first and second conductive contacts having inwardly curved cross-sectional widths in the semiconductor substrate.
- 10. The semiconductor device as claimed in claim 9 wherein the conductive contacts have the inwardly curved cross-sectional widths with top widths and subsurface widths in the semiconductor substrate, the sub-surface widths are less than about 50% of the widths of the top widths.
- 11. The semiconductor device as claimed in claim 9 wherein the first and second conductive contacts have the inwardly curved cross-sectional widths with top widths and sub-surface widths in the semiconductor substrate, the sub-surface widths are between about 50% and about 10% of the widths of the top widths.
- 12. The semiconductor device as claimed in claim 9 including a dielectric layer over the semiconductor substrate having the first and second conductive contact extending therethrough, the first and second conductive contacts having widths in the dielectric layer equal to the widths of the top widths thereof at the surface of the semiconductor substrate.
- 13. The semiconductor device as claimed in claim 9 wherein the first and second contact trenches are lined with a metal silicide.
- 14. The semiconductor device as claimed in claim 9 wherein the first and second source/drain junctions include first and second extension source/drain junctions in the silicon substrate, the first and second extension source/drain junctions are closest together below the surface of the silicon substrate.
- 15. The semiconductor device as claimed in claim 9 including:
an insulator layer disposed below the silicon substrate to form a silicon on insulator structure; and a further silicon substrate disposed below the insulator layer.
- 16. The semiconductor device as claimed in claim 9 including an isolation trench disposed around the first and second source/drain junctions and the first and second contact trenches, the isolation trench disposed in the silicon substrate.
- 17. A method of manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate; forming a gate dielectric layer over the semiconductor substrate; forming a gate layer over the gate dielectric layer; etching the gate dielectric layer and the gate layer to form a gate stack; implanting source/drain junctions adjacent the sides of the gate stack; forming contact trenches in the semiconductor substrate to expose the source/drain junctions, the contact trenches adjacent the opposite sides of the gate stack, the contact trenches having inwardly curved cross-sectional widths; and forming conductive contacts in the contact trenches conductively connected with the source/drain junctions, the conductive contacts having inwardly curved cross-sectional widths in the semiconductor substrate.
- 18. The method of manufacturing a semiconductor device as claimed in claim 17 wherein the forming the conductive contacts forms the inwardly curved cross-sectional widths with top widths and sub-surface widths in the semiconductor substrate, the sub-surface widths are less than about 50% of the widths of the top widths.
- 19. The method of manufacturing a semiconductor device as claimed in claim 17 wherein the step of forming the conductive contacts forms the inwardly curved cross-sectional widths with top width and sub-surface widths in the semiconductor substrate, the sub-surface widths are between about 50% and about 10% of the widths of the top widths.
- 20. The method of manufacturing a semiconductor device as claimed in claim 17 including depositing a dielectric layer over the semiconductor substrate having the conductive contacts extending therethrough, the conductive contacts having widths in the dielectric layer equal to the top widths thereof at the surface of the semiconductor substrate and self-aligned on the contact trenches.
- 21. The method of manufacturing a semiconductor device as claimed in claim 17 including lining the contact trenches with a salicide.
- 22. The method of manufacturing a semiconductor device as claimed in claim 17 wherein the forming the source/drain junctions include forming extension source/drain junctions in the semiconductor substrate and forming the extension source/drain junctions closest together below the surface of the semiconductor substrate.
- 23. The method of manufacturing a semiconductor device as claimed in claim 17 including:
providing a further semiconductor substrate; and forming an insulator layer on the further semiconductor substrate for the semiconductor substrate to be formed on to form a semiconductor on insulator structure.
- 24. The method of manufacturing a semiconductor device as claimed in claim 17 including forming an isolation insulator around the source/drain junctions and the contact trenches, the isolation insulator formed in the semiconductor substrate.
- 25. A method of manufacturing a semiconductor device, comprising the steps of:
providing a silicon substrate; forming a gate oxide layer over the silicon substrate; forming a polysilicon gate layer over the gate oxide layer; etching the gate oxide layer and the polysilicon gate layer to form a gate stack; implanting source/drain junctions adjacent the sides of the gate stack; forming contact trenches in the silicon substrate to expose the source/drain junctions, the contact trenches adjacent the opposite sides of the gate stack, the contact trenches having inwardly curved cross-sectional widths in the semiconductor substrate; and forming conductive contacts in the contact trenches in conductive connection with the source/drain junctions, the conductive contacts having inwardly curved cross-sectional widths in the semiconductor substrate.
- 26. The method of manufacturing a semiconductor device as claimed in claim 25 wherein the forming the conductive contacts forms the inwardly curved cross-sectional widths with top widths and sub-surface widths in the semiconductor substrate, the sub-surface widths are less than about 50% of the widths of the top widths.
- 27. The method of manufacturing a semiconductor device as claimed in claim 25 wherein the forming of the conductive contacts forms the inwardly curved cross-sectional widths with top widths and sub-surface widths in the semiconductor substrate, the sub-surface widths are between about 50% and about 10% of the widths of the top widths.
- 28. The method of manufacturing a semiconductor device as claimed in claim 25 including forming a dielectric layer over the semiconductor substrate having the conductive contacts extending therethrough, the conductive contact having widths in the dielectric layer equal to the widths of the top widths thereof at the surface of the semiconductor substrate and self-aligned on the contact trenches.
- 29. The method of manufacturing a semiconductor device as claimed in claim 25 including lining the contact trenches with a metal silicide.
- 30. The method of manufacturing a semiconductor device as claimed in claim 25 wherein the forming the source/drain junctions include forming extension source/drain junctions in the silicon substrate around the contact trenches, the extension source/drain junctions are formed closest together below the surface of the silicon substrate.
- 31. The method of manufacturing a semiconductor device as claimed in claim 25 including:
providing an insulator layer disposed below the silicon substrate to form a silicon on insulator structure; and providing a further silicon substrate disposed below the insulator layer.
- 32. The method of manufacturing a semiconductor device as claimed in claim 25 including forming an isolation trench around the source/drain junctions and the contact trenches, the isolation trench formed in the silicon substrate.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This is a Continuation-in-Part of co-pending application Ser. No. 09/510,102 filed Feb. 22, 2000.
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09510102 |
Feb 2000 |
US |
Child |
10167095 |
Jun 2002 |
US |