Sanjay Dhar

Person

Lake Oswego, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Concurrent optimization of timing, area, and leakage power
- Patent number 9,245,075
- Issue date Jan 26, 2016
- Synopsys, Inc.
- Yiu-Chung Mang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Look-up based buffer tree synthesis
- Patent number 9,189,583
- Issue date Nov 17, 2015
- Synopsys, Inc.
- Sanjay Dhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic clock tree routing rule generation
- Patent number 9,009,645
- Issue date Apr 14, 2015
- Synopsys, Inc.
- Aiqun Cao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Look-up based fast logic synthesis
- Patent number 8,924,901
- Issue date Dec 30, 2014
- Synopsys, Inc.
- Yiu-Chung Mang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incremental clock tree synthesis
- Patent number 8,869,091
- Issue date Oct 21, 2014
- Synopsys, Inc.
- Sanjay Dhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Manufacturability
- Patent number 8,555,212
- Issue date Oct 8, 2013
- Mentor Graphics Corporation
- Joseph D Sawicki
- G05 - CONTROLLING REGULATING
Information Patent Grant
Manufacturability
- Patent number 8,375,337
- Issue date Feb 12, 2013
- Mentor Graphics Corporation
- Joseph D Sawicki
Information Patent Grant
Circuit simulation using dynamic partitioning and on-demand evaluation
- Patent number 6,480,816
- Issue date Nov 12, 2002
- Sanjay Dhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Switch level simulation employing dynamic short-circuit ratio
- Patent number 5,703,798
- Issue date Dec 30, 1997
- Mentor Graphics Corporation
- Sanjay Dhar
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CONCURRENT OPTIMIZATION OF TIMING, AREA, AND LEAKAGE POWER
- Publication number 20150089462
- Publication date Mar 26, 2015
- Synopsys, Inc.
- Yiu-Chung Mang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-CHIP-VARIATION (OCV) AND TIMING-CRITICALITY AWARE CLOCK TREE SYN...
- Publication number 20140289690
- Publication date Sep 25, 2014
- Synopsys, Inc.
- Kaviraj Chopra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOOK-UP BASED FAST LOGIC SYNTHESIS
- Publication number 20140237437
- Publication date Aug 21, 2014
- Synopsys, Inc.
- Yiu-Chung Mang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREMENTAL CLOCK TREE SYNTHESIS
- Publication number 20140189627
- Publication date Jul 3, 2014
- Synopsys, Inc.
- Sanjay Dhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC CLOCK TREE ROUTING RULE GENERATION
- Publication number 20140181777
- Publication date Jun 26, 2014
- Synopsys, Inc.
- Aiqun Cao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOOK-UP BASED BUFFER TREE SYNTHESIS
- Publication number 20140181765
- Publication date Jun 26, 2014
- Synopsys, Inc.
- Sanjay Dhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Manufacturability
- Publication number 20140040850
- Publication date Feb 6, 2014
- Mentor Graphics Corporation
- Joseph Sawicki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Manufacturability
- Publication number 20090235209
- Publication date Sep 17, 2009
- Mentor Graphics Corporation
- Joseph D. Sawicki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Defect location identification for microdevice manufacturing and test
- Publication number 20060069958
- Publication date Mar 30, 2006
- Joseph D. Sawicki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design for manufacturability
- Publication number 20050234684
- Publication date Oct 20, 2005
- Mentor Graphics Corp.
- Joseph D. Sawicki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design for manufacturability
- Publication number 20050015740
- Publication date Jan 20, 2005
- Mentor Graphics Corp.
- Joseph D. Sawicki
- G06 - COMPUTING CALCULATING COUNTING

Sanjay Dhar

Person

Patents Grantslast 30 patents

Concurrent optimization of timing, area, and leakage power

Look-up based buffer tree synthesis

Automatic clock tree routing rule generation

Look-up based fast logic synthesis

Incremental clock tree synthesis

Manufacturability

Manufacturability

Circuit simulation using dynamic partitioning and on-demand evaluation

Switch level simulation employing dynamic short-circuit ratio

Patents Applicationslast 30 patents

CONCURRENT OPTIMIZATION OF TIMING, AREA, AND LEAKAGE POWER

ON-CHIP-VARIATION (OCV) AND TIMING-CRITICALITY AWARE CLOCK TREE SYN...

LOOK-UP BASED FAST LOGIC SYNTHESIS

INCREMENTAL CLOCK TREE SYNTHESIS

AUTOMATIC CLOCK TREE ROUTING RULE GENERATION

LOOK-UP BASED BUFFER TREE SYNTHESIS

Manufacturability

Manufacturability

Defect location identification for microdevice manufacturing and test

Design for manufacturability

Design for manufacturability