Sanjay R. Deshpande

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Data processing system having a coherency interconnect
- Patent number 10,628,329
- Issue date Apr 21, 2020
- NXP USA, INC.
- Sanjay R. Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing system having a write request network and a write d...
- Patent number 10,346,089
- Issue date Jul 9, 2019
- NXP USA, INC.
- Sanjay R. Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed reservation based coherency protocol
- Patent number 10,114,748
- Issue date Oct 30, 2018
- NXP USA, INC.
- Sanjay R. Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coherent memory interleaving with uniform latency
- Patent number 9,977,750
- Issue date May 22, 2018
- NXP USA, INC.
- Sanjay R. Deshpande
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Least recently used (LRU) cache replacement implementation using a...
- Patent number 9,720,847
- Issue date Aug 1, 2017
- NXP USA, INC.
- Thang Q. Nguyen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for controlling ordered write transactions to m...
- Patent number 9,665,518
- Issue date May 30, 2017
- NXP USA, INC.
- Sanjay R. Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient coherency response mechanism
- Patent number 9,632,933
- Issue date Apr 25, 2017
- NXP USA, INC.
- Sanjay R. Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Switch point having look-ahead bypass
- Patent number 9,497,141
- Issue date Nov 15, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Thang Q. Nguyen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Piggy-back snoops for non-coherent memory transactions within distr...
- Patent number 9,448,741
- Issue date Sep 20, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Sanjay R. Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for processing potentially self-inconsistent memo...
- Patent number 9,026,742
- Issue date May 5, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Sanjay R. Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tracing support for interconnect fabric
- Patent number 8,990,633
- Issue date Mar 24, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Zheng Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flow control mechanisms for avoidance of retries and/or deadlocks i...
- Patent number 8,554,967
- Issue date Oct 8, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Sanjay Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Access management technique with operation translation capability
- Patent number 8,473,644
- Issue date Jun 25, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Sanjay Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interprocessor message transmission via coherency-based interconnect
- Patent number 7,941,499
- Issue date May 10, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Becky G. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for transaction tag assignment and maintenance...
- Patent number 7,529,799
- Issue date May 5, 2009
- International Business Machines Corporation
- Manuel Joseph Alvarez, II
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for reporting cache coherency state retained with...
- Patent number 7,502,893
- Issue date Mar 10, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Sanjay R. Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for achieving correct order among bus memory t...
- Patent number 6,779,036
- Issue date Aug 17, 2004
- International Business Machines Corporation
- Sanjay Raghunath Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for controlling data transfers with physical sepa...
- Patent number 6,725,307
- Issue date Apr 20, 2004
- International Business Machines Corporation
- Manuel Joseph Alvarez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to distribute interrupts to multiple interrupt...
- Patent number 6,606,676
- Issue date Aug 12, 2003
- International Business Machines Corporation
- Sanjay Raghunath Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for resolution of transaction collisions to achie...
- Patent number 6,591,348
- Issue date Jul 8, 2003
- International Business Machines Corporation
- Sanjay Raghunath Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing remstat protocol under inclusion...
- Patent number 6,587,930
- Issue date Jul 1, 2003
- International Business Machines Corporation
- Sanjay Raghunath Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for transaction pacing to reduce destructive i...
- Patent number 6,516,379
- Issue date Feb 4, 2003
- International Business Machines Corporation
- Sanjay Raghunath Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transfer of data between processors in a multi-processor system
- Patent number 6,484,220
- Issue date Nov 19, 2002
- International Business Machines Corporation
- Manuel Joseph Alvarez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus using a distributed system structure to suppor...
- Patent number 6,467,012
- Issue date Oct 15, 2002
- International Business Machines Corporation
- Manuel Alvarez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for bypass prefetch data path
- Patent number 6,449,698
- Issue date Sep 10, 2002
- International Business Machines Corporation
- Sanjay Raghunath Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing global coherence in SMP systems using response combinatio...
- Patent number 6,442,597
- Issue date Aug 27, 2002
- International Business Machines Corporation
- Sanjay Raghunath Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arbitration protocol for peer-to-peer communication in synchronous...
- Patent number 6,434,638
- Issue date Aug 13, 2002
- International Business Machines Corporation
- Sanjay Raghunath Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for reissuing load requests in a multi-stream pre...
- Patent number 6,317,811
- Issue date Nov 13, 2001
- International Business Machines Corporation
- Sanjay Raghunath Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing multiple interrupt controller...
- Patent number 5,802,377
- Issue date Sep 1, 1998
- International Business Machines Corp.
- Sanjay Raghunath Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive scalable cache coherence network for a multiprocessor data...
- Patent number 5,781,757
- Issue date Jul 14, 1998
- International Business Machines Corporation
- Sanjay Raghunath Deshpande
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DISTRIBUTED RESERVATION BASED COHERENCY PROTOCOL
- Publication number 20180089083
- Publication date Mar 29, 2018
- FREESCALE SEMICONDUCTOR, INC.
- SANJAY R. DESHPANDE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSING SYSTEM HAVING A COHERENCY INTERCONNECT
- Publication number 20170308404
- Publication date Oct 26, 2017
- FREESCALE SEMICONDUCTOR, INC.
- SANJAY R. DESHPANDE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSING SYSTEM HAVING A WRITE REQUEST NETWORK AND A WRITE D...
- Publication number 20170249103
- Publication date Aug 31, 2017
- FREESCALE SEMICONDUCTOR, INC.
- Sanjay R. DESHPANDE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SWITCH POINT HAVING LOOK-AHEAD BYPASS
- Publication number 20160241492
- Publication date Aug 18, 2016
- FREESCALE SEMICONDUCTOR, INC.
- THANG Q. NGUYEN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
EFFICIENT COHERENCY RESPONSE MECHANISM
- Publication number 20160224468
- Publication date Aug 4, 2016
- FREESCALE SEMICONDUCTOR, INC.
- SANJAY R. DESHPANDE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COHERENT MEMORY INTERLEAVING WITH UNIFORM LATENCY
- Publication number 20160170916
- Publication date Jun 16, 2016
- FREESCALE SEMICONDUCTOR, INC.
- SANJAY R. DESHPANDE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods And Systems For Controlling Ordered Write Transactions To M...
- Publication number 20160085706
- Publication date Mar 24, 2016
- Sanjay R. Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Piggy-Back Snoops For Non-Coherent Memory Transactions Within Distr...
- Publication number 20160085478
- Publication date Mar 24, 2016
- Sanjay R. Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEAST RECENTLY USED (LRU) CACHE REPLACEMENT IMPLEMENTATION USING A...
- Publication number 20150026410
- Publication date Jan 22, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Thang Q. Nguyen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flow Control Mechanisms for Avoidance of Retries and/or Deadlocks i...
- Publication number 20100318713
- Publication date Dec 16, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Sanjay Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRACING SUPPORT FOR INTERCONNECT FABRIC
- Publication number 20100268990
- Publication date Oct 21, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Zheng Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCESS MANAGEMENT TECHNIQUE WITH OPERATION TRANSLATION CAPABILITY
- Publication number 20100228945
- Publication date Sep 9, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Sanjay Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCESS MANAGEMENT TECHNIQUE FOR STORAGE-EFFICIENT MAPPING BETWEEN I...
- Publication number 20100228943
- Publication date Sep 9, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Sanjay Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR PROCESSING POTENTIALLY SELF-INCONSISTENT MEMO...
- Publication number 20090164737
- Publication date Jun 25, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Sanjay R. Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECIFICATION OF COHERENCE DOMAIN DURING ADDRESS TRANSLATION
- Publication number 20090019232
- Publication date Jan 15, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Sanjay R. Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERPROCESSOR MESSAGE TRANSMISSION VIA COHERENCY-BASED INTERCONNECT
- Publication number 20080222389
- Publication date Sep 11, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Becky G. Bruce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR REPORTING CACHE COHERENCY STATE RETAINED WITH...
- Publication number 20080104330
- Publication date May 1, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Sanjay R. Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for implementing remstat protocol under inclusion...
- Publication number 20030120874
- Publication date Jun 26, 2003
- Sanjay Raghunath Deshpande
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for transaction tag assignment and maintenance...
- Publication number 20030046356
- Publication date Mar 6, 2003
- Manuel Joseph Alvarez
- G06 - COMPUTING CALCULATING COUNTING

Sanjay R. Deshpande

Person

Patents Grantslast 30 patents

Data processing system having a coherency interconnect

Data processing system having a write request network and a write d...

Distributed reservation based coherency protocol

Coherent memory interleaving with uniform latency

Least recently used (LRU) cache replacement implementation using a...

Methods and systems for controlling ordered write transactions to m...

Efficient coherency response mechanism

Switch point having look-ahead bypass

Piggy-back snoops for non-coherent memory transactions within distr...

System and method for processing potentially self-inconsistent memo...

Tracing support for interconnect fabric

Flow control mechanisms for avoidance of retries and/or deadlocks i...

Access management technique with operation translation capability

Interprocessor message transmission via coherency-based interconnect

Method and apparatus for transaction tag assignment and maintenance...

System and method for reporting cache coherency state retained with...

Method and apparatus for achieving correct order among bus memory t...

Method and system for controlling data transfers with physical sepa...

Method and apparatus to distribute interrupts to multiple interrupt...

Method and system for resolution of transaction collisions to achie...

Method and system for implementing remstat protocol under inclusion...

Method and apparatus for transaction pacing to reduce destructive i...

Transfer of data between processors in a multi-processor system

Method and apparatus using a distributed system structure to suppor...

Method and system for bypass prefetch data path

Providing global coherence in SMP systems using response combinatio...

Arbitration protocol for peer-to-peer communication in synchronous...

Method and system for reissuing load requests in a multi-stream pre...

Method and apparatus for implementing multiple interrupt controller...

Adaptive scalable cache coherence network for a multiprocessor data...

Patents Applicationslast 30 patents

DISTRIBUTED RESERVATION BASED COHERENCY PROTOCOL

DATA PROCESSING SYSTEM HAVING A COHERENCY INTERCONNECT

DATA PROCESSING SYSTEM HAVING A WRITE REQUEST NETWORK AND A WRITE D...

SWITCH POINT HAVING LOOK-AHEAD BYPASS

EFFICIENT COHERENCY RESPONSE MECHANISM

COHERENT MEMORY INTERLEAVING WITH UNIFORM LATENCY

Methods And Systems For Controlling Ordered Write Transactions To M...

Piggy-Back Snoops For Non-Coherent Memory Transactions Within Distr...

LEAST RECENTLY USED (LRU) CACHE REPLACEMENT IMPLEMENTATION USING A...

Flow Control Mechanisms for Avoidance of Retries and/or Deadlocks i...

TRACING SUPPORT FOR INTERCONNECT FABRIC

ACCESS MANAGEMENT TECHNIQUE WITH OPERATION TRANSLATION CAPABILITY

ACCESS MANAGEMENT TECHNIQUE FOR STORAGE-EFFICIENT MAPPING BETWEEN I...

SYSTEM AND METHOD FOR PROCESSING POTENTIALLY SELF-INCONSISTENT MEMO...

SPECIFICATION OF COHERENCE DOMAIN DURING ADDRESS TRANSLATION

INTERPROCESSOR MESSAGE TRANSMISSION VIA COHERENCY-BASED INTERCONNECT

SYSTEM AND METHOD FOR REPORTING CACHE COHERENCY STATE RETAINED WITH...

Method and system for implementing remstat protocol under inclusion...

Method and apparatus for transaction tag assignment and maintenance...