Sanjay S. Talreja

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Power saving in NAND flash memory
- Patent number 8,489,780
- Issue date Jul 16, 2013
- Intel Corporation
- Rajesh Sundaram
- G11 - INFORMATION STORAGE
Information Patent Grant
Status register architecture for flexible read-while-write device
- Patent number 6,931,498
- Issue date Aug 16, 2005
- Intel Corporation
- Sanjay S. Talreja
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system to retrieve information
- Patent number 6,920,539
- Issue date Jul 19, 2005
- Intel Corporation
- Shekoufeh Qawami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Burst suspend and resume with computer memory
- Patent number 6,618,790
- Issue date Sep 9, 2003
- Intel Corporation
- Sanjay S. Talreja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multilevel cell memory architecture
- Patent number 6,587,373
- Issue date Jul 1, 2003
- Intel Corporation
- Sanjay S. Talreja
- G11 - INFORMATION STORAGE
Information Patent Grant
Multilevel cell memory architecture
- Patent number 6,483,743
- Issue date Nov 19, 2002
- Intel Corporation
- Sanjay S. Talreja
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for preventing the fraudulent use of a cellula...
- Patent number 6,223,290
- Issue date Apr 24, 2001
- Intel Corporation
- Robert E. Larsen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus and method using volatile lock and lock-down registers an...
- Patent number 6,154,819
- Issue date Nov 28, 2000
- Intel Corporation
- Robert E. Larsen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic single bit per cell to multiple bit per cell memory
- Patent number 6,097,637
- Issue date Aug 1, 2000
- Intel Corporation
- Mark E. Bauer
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory partitioning for read-while-write operation
- Patent number 6,088,264
- Issue date Jul 11, 2000
- Intel Corporation
- Peter K. Hazen
- G11 - INFORMATION STORAGE
Information Patent Grant
Controlling flash memory program and erase pulses
- Patent number 5,944,837
- Issue date Aug 31, 1999
- Intel Corporation
- Sanjay S. Talreja
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-configuring interface architecture on flash memories
- Patent number 5,933,026
- Issue date Aug 3, 1999
- Intel Corporation
- Robert E. Larsen
- G11 - INFORMATION STORAGE
Information Patent Grant
Controlling flash memory program and erase pulses
- Patent number 5,907,700
- Issue date May 25, 1999
- Intel Corporation
- Sanjay S. Talreja
- G11 - INFORMATION STORAGE
Information Patent Grant
Input/output power supply detection scheme for flash memory
- Patent number 5,896,338
- Issue date Apr 20, 1999
- Intel Corporation
- Marcus E. Landgraf
- G11 - INFORMATION STORAGE
Information Patent Grant
Sensing scheme for flash memory with multilevel cells
- Patent number 5,828,616
- Issue date Oct 27, 1998
- Intel Corporation
- Mark E. Bauer
- G11 - INFORMATION STORAGE
Information Patent Grant
Sensing scheme for flash memory with multilevel cells
- Patent number 5,748,546
- Issue date May 5, 1998
- Intel Corporation
- Mark E. Bauer
- G11 - INFORMATION STORAGE
Information Patent Grant
Hardware reset of a write state machine for flash memory
- Patent number 5,742,787
- Issue date Apr 21, 1998
- Intel Corporation
- Sanjay S. Talreja
- G11 - INFORMATION STORAGE
Information Patent Grant
Auto-verification of programming flash memory cells
- Patent number 5,684,741
- Issue date Nov 4, 1997
- Intel Corporation
- Sanjay Talreja
- G11 - INFORMATION STORAGE
Information Patent Grant
Write verify schemes for flash memory with multilevel cells
- Patent number 5,539,690
- Issue date Jul 23, 1996
- Intel Corporation
- Sanjay S. Talreja
- G11 - INFORMATION STORAGE
Information Patent Grant
Drain bias multiplexing for multiple bit flash cell
- Patent number 5,485,422
- Issue date Jan 16, 1996
- Intel Corporation
- Mark E. Bauer
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable redundancy scheme suitable for single-bit state and mu...
- Patent number 5,438,546
- Issue date Aug 1, 1995
- Intel Corporation
- Michel I. Ishac
- G11 - INFORMATION STORAGE
Information Patent Grant
User selectable word/byte input architecture for flash EEPROM memor...
- Patent number 5,379,413
- Issue date Jan 3, 1995
- Intel Corporation
- Peter K. Hazen
- G11 - INFORMATION STORAGE
Information Patent Grant
Gate/source disturb protection for sixteen-bit flash EEPROM memory...
- Patent number 5,317,535
- Issue date May 31, 1994
- Intel Corporation
- Sanjay S. Talreja
- G11 - INFORMATION STORAGE
Information Patent Grant
Floating gate nonvolatile memory with configurable erasure blocks
- Patent number 5,280,447
- Issue date Jan 18, 1994
- Intel Corporation
- Peter K. Hazen
- G11 - INFORMATION STORAGE
Information Patent Grant
Floating gate nonvolatile memory with distributed blocking feature
- Patent number 5,267,196
- Issue date Nov 30, 1993
- Intel Corporation
- Sanjay S. Talreja
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Power saving in NAND flash memory
- Publication number 20080155287
- Publication date Jun 26, 2008
- Rajesh Sundaram
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory management apparatus, systems, and methods
- Publication number 20060143371
- Publication date Jun 29, 2006
- John C. Rudelic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system to retrieve information
- Publication number 20040003192
- Publication date Jan 1, 2004
- Shekoufeh Qawami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multilevel cell memory architecture
- Publication number 20030031050
- Publication date Feb 13, 2003
- Sanjay S. Talreja
- G11 - INFORMATION STORAGE
Information Patent Application
Status register architecture for flexible read-while-write device
- Publication number 20020144066
- Publication date Oct 3, 2002
- Sanjay S. Talreja
- G11 - INFORMATION STORAGE

Sanjay S. Talreja

Person

Patents Grantslast 30 patents

Power saving in NAND flash memory

Status register architecture for flexible read-while-write device

Method and system to retrieve information

Burst suspend and resume with computer memory

Multilevel cell memory architecture

Multilevel cell memory architecture

Method and apparatus for preventing the fraudulent use of a cellula...

Apparatus and method using volatile lock and lock-down registers an...

Dynamic single bit per cell to multiple bit per cell memory

Flash memory partitioning for read-while-write operation

Controlling flash memory program and erase pulses

Self-configuring interface architecture on flash memories

Controlling flash memory program and erase pulses

Input/output power supply detection scheme for flash memory

Sensing scheme for flash memory with multilevel cells

Sensing scheme for flash memory with multilevel cells

Hardware reset of a write state machine for flash memory

Auto-verification of programming flash memory cells

Write verify schemes for flash memory with multilevel cells

Drain bias multiplexing for multiple bit flash cell

Programmable redundancy scheme suitable for single-bit state and mu...

User selectable word/byte input architecture for flash EEPROM memor...

Gate/source disturb protection for sixteen-bit flash EEPROM memory...

Floating gate nonvolatile memory with configurable erasure blocks

Floating gate nonvolatile memory with distributed blocking feature

Patents Applicationslast 30 patents

Power saving in NAND flash memory

Integrated memory management apparatus, systems, and methods

Method and system to retrieve information

Multilevel cell memory architecture

Status register architecture for flexible read-while-write device