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Sanjay Sengupta
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San Jose, CA, US
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Patents Grants
last 30 patents
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Patent Grant
Dft technique for avoiding contention/conflict in logic built-in se...
Patent number
7,096,397
Issue date
Aug 22, 2006
Intel Corporation
Sandip Kundu
G11 - INFORMATION STORAGE
Information
Patent Grant
Generalized fault model for defects and circuit marginalities
Patent number
7,036,063
Issue date
Apr 25, 2006
Intel Corporation
Sandip Kundu
G11 - INFORMATION STORAGE
Information
Patent Grant
Constrained signature-based test
Patent number
6,510,398
Issue date
Jan 21, 2003
Intel Corporation
Sandip Kundu
G01 - MEASURING TESTING
Information
Patent Grant
Method and apparatus for performing register transfer level scan se...
Patent number
6,237,121
Issue date
May 22, 2001
Intel Corporation
Sitaram Yadavalli
G01 - MEASURING TESTING
Patents Applications
last 30 patents
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Patent Application
Generalized fault model for defects and circuit marginalities
Publication number
20040205436
Publication date
Oct 14, 2004
Sandip Kundu
G01 - MEASURING TESTING
Information
Patent Application
Generalized fault model for defects and circuit marginalities
Publication number
20040064773
Publication date
Apr 1, 2004
Sandip Kundu
G01 - MEASURING TESTING
Information
Patent Application
Dft technique for avoiding contention/conflict in logic built-in se...
Publication number
20030053358
Publication date
Mar 20, 2003
Intel Corporation
Sandip Kundu
G11 - INFORMATION STORAGE