SANJEEV S. JAHAGIRDAR

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Instructions and logic to perform floating point and integer operat...
- Patent number 12,217,053
- Issue date Feb 4, 2025
- Intel Corporation
- Himanshu Kaul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient thread group scheduling
- Patent number 12,210,900
- Issue date Jan 28, 2025
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for cache optimization
- Patent number 12,182,035
- Issue date Dec 31, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for error detection and control for embedded me...
- Patent number 12,147,302
- Issue date Nov 19, 2024
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instructions and logic to perform floating point and integer operat...
- Patent number 12,141,578
- Issue date Nov 12, 2024
- Intel Corporation
- Himanshu Kaul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enabling product SKUs based on chiplet configurations
- Patent number 12,141,890
- Issue date Nov 12, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for cache optimization
- Patent number 12,124,383
- Issue date Oct 22, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disaggregation of system-on-chip (SOC) architecture
- Patent number 12,112,398
- Issue date Oct 8, 2024
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Regional adjustment of render rate
- Patent number 12,061,831
- Issue date Aug 13, 2024
- Intel Corporation
- Eric J. Asperheim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disaggregation of system-on-chip (SOC) architecture
- Patent number 12,056,789
- Issue date Aug 6, 2024
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for cache optimization
- Patent number 12,056,059
- Issue date Aug 6, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instructions and logic to perform floating point and integer operat...
- Patent number 12,039,331
- Issue date Jul 16, 2024
- Intel Corporation
- Himanshu Kaul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Barriers and synchronization for machine learning at autonomous mac...
- Patent number 12,001,209
- Issue date Jun 4, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic power budget allocation in multi-processor system
- Patent number 11,874,715
- Issue date Jan 16, 2024
- Intel Corporation
- Nikos Kaburlasos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processing unit processing and caching improvements
- Patent number 11,861,761
- Issue date Jan 2, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Regional adjustment of render rate
- Patent number 11,816,384
- Issue date Nov 14, 2023
- Intel Corporation
- Eric J. Asperheim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic distributed training of machine learning models
- Patent number 11,797,837
- Issue date Oct 24, 2023
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid low power homogenous grapics processing units
- Patent number 11,762,696
- Issue date Sep 19, 2023
- Intel Corporation
- Abhishek R Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disaggregation of system-on-chip (SOC) architecture
- Patent number 11,763,416
- Issue date Sep 19, 2023
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disaggregation of system-on-chip (SOC) architecture
- Patent number 11,756,150
- Issue date Sep 12, 2023
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data operations and finite state machine for machine learning via b...
- Patent number 11,748,106
- Issue date Sep 5, 2023
- Intel Corporation
- Liwei Ma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coordination and increased utilization of graphics processors durin...
- Patent number 11,748,841
- Issue date Sep 5, 2023
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic precision for neural network compute operations
- Patent number 11,748,606
- Issue date Sep 5, 2023
- Intel Corporation
- Kamal Sinha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instructions and logic to perform floating point and integer operat...
- Patent number 11,720,355
- Issue date Aug 8, 2023
- Intel Corporation
- Himanshu Kaul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling power delivery to a processor via a bypass
- Patent number 11,687,135
- Issue date Jun 27, 2023
- Tahoe Research, LTD.
- Sanjeev S. Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive multibit bus for energy optimization
- Patent number 11,636,831
- Issue date Apr 25, 2023
- Intel Corporation
- Sanjeev S. Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storage management for machine learning at autonomous machines
- Patent number 11,592,817
- Issue date Feb 28, 2023
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Regional adjustment of render rate
- Patent number 11,531,510
- Issue date Dec 20, 2022
- Intel Corporation
- Eric J. Asperheim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic power budget allocation in multi-processor system
- Patent number 11,493,974
- Issue date Nov 8, 2022
- Intel Corporation
- Nikos Kaburlasos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method of balancing input power from multiple sources
- Patent number 11,474,547
- Issue date Oct 18, 2022
- Intel Corporation
- Darryl Tschirhart
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
- Publication number 20250061535
- Publication date Feb 20, 2025
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Regional Adjustment of Render Rate
- Publication number 20240354043
- Publication date Oct 24, 2024
- Intel Corporation
- Eric J. Asperheim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BARRIERS AND SYNCHRONIZATION FOR MACHINE LEARNING AT AUTONOMOUS MAC...
- Publication number 20240280987
- Publication date Aug 22, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERAT...
- Publication number 20240184572
- Publication date Jun 6, 2024
- Intel Corporation
- Himanshu Kaul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Regional Adjustment of Render Rate
- Publication number 20240086138
- Publication date Mar 14, 2024
- Intel Corporation
- Eric J. Asperheim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSING UNIT PROCESSING AND CACHING IMPROVEMENTS
- Publication number 20240078630
- Publication date Mar 7, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COORDINATION AND INCREASED UTILIZATION OF GRAPHICS PROCESSORS DURIN...
- Publication number 20240013337
- Publication date Jan 11, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
- Publication number 20240013338
- Publication date Jan 11, 2024
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
- Publication number 20240005443
- Publication date Jan 4, 2024
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC PRECISION FOR NEURAL NETWORK COMPUTE OPERATIONS
- Publication number 20240005136
- Publication date Jan 4, 2024
- Intel Corporation
- Kamal Sinha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID LOW POWER HOMOGENOUS GRAPICS PROCESSING UNITS
- Publication number 20240004713
- Publication date Jan 4, 2024
- Intel Corporation
- Abhishek R Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC DISTRIBUTED TRAINING OF MACHINE LEARNING MODELS
- Publication number 20230334316
- Publication date Oct 19, 2023
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSING UNIT PROCESSING AND CACHING IMPROVEMENTS
- Publication number 20230260075
- Publication date Aug 17, 2023
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Regional Adjustment of Render Rate
- Publication number 20230142472
- Publication date May 11, 2023
- Intel Corporation
- Eric J. Asperheim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERAT...
- Publication number 20230046506
- Publication date Feb 16, 2023
- Intel Corporation
- Himanshu Kaul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC POWER BUDGET ALLOCATION IN MULTI-PROCESSOR SYSTEM
- Publication number 20230030396
- Publication date Feb 2, 2023
- Intel Corporation
- Nikos Kaburlasos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COORDINATION AND INCREASED UTILIZATION OF GRAPHICS PROCESSORS DURIN...
- Publication number 20220366527
- Publication date Nov 17, 2022
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BARRIERS AND SYNCHRONIZATION FOR MACHINE LEARNING AT AUTONOMOUS MAC...
- Publication number 20220357742
- Publication date Nov 10, 2022
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERAT...
- Publication number 20220357945
- Publication date Nov 10, 2022
- Intel Corporation
- Himanshu Kaul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR CACHE OPTIMIZATION
- Publication number 20220350751
- Publication date Nov 3, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT THREAD GROUP SCHEDULING
- Publication number 20220350651
- Publication date Nov 3, 2022
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA OPERATIONS AND FINITE STATE MACHINE FOR MACHINE LEARNING VIA B...
- Publication number 20220253317
- Publication date Aug 11, 2022
- Intel Corporation
- Liwei Ma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID LOW POWER HOMOGENOUS GRAPICS PROCESSING UNITS
- Publication number 20220206853
- Publication date Jun 30, 2022
- Intel Corporation
- Abhishek R Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENABLING PRODUCT SKUS BASED ON CHIPLET CONFIGURATIONS
- Publication number 20220188967
- Publication date Jun 16, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
- Publication number 20220180468
- Publication date Jun 9, 2022
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR CACHE OPTIMIZATION
- Publication number 20220156202
- Publication date May 19, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR CACHE OPTIMIZATION
- Publication number 20220114108
- Publication date Apr 14, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Regional Adjustment of Render Rate
- Publication number 20220066726
- Publication date Mar 3, 2022
- Intel Corporation
- Eric J. Asperheim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE MULTIBIT BUS FOR ENERGY OPTIMIZATION
- Publication number 20220044656
- Publication date Feb 10, 2022
- Intel Corporation
- Sanjeev S. Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
- Publication number 20220036500
- Publication date Feb 3, 2022
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING

SANJEEV S. JAHAGIRDAR

Person

Patents Grantslast 30 patents

Instructions and logic to perform floating point and integer operat...

Efficient thread group scheduling

Systems and methods for cache optimization

Systems and methods for error detection and control for embedded me...

Instructions and logic to perform floating point and integer operat...

Enabling product SKUs based on chiplet configurations

Systems and methods for cache optimization

Disaggregation of system-on-chip (SOC) architecture

Regional adjustment of render rate

Disaggregation of system-on-chip (SOC) architecture

Systems and methods for cache optimization

Instructions and logic to perform floating point and integer operat...

Barriers and synchronization for machine learning at autonomous mac...

Dynamic power budget allocation in multi-processor system

Graphics processing unit processing and caching improvements

Regional adjustment of render rate

Dynamic distributed training of machine learning models

Hybrid low power homogenous grapics processing units

Disaggregation of system-on-chip (SOC) architecture

Disaggregation of system-on-chip (SOC) architecture

Data operations and finite state machine for machine learning via b...

Coordination and increased utilization of graphics processors durin...

Dynamic precision for neural network compute operations

Instructions and logic to perform floating point and integer operat...

Controlling power delivery to a processor via a bypass

Adaptive multibit bus for energy optimization

Storage management for machine learning at autonomous machines

Regional adjustment of render rate

Dynamic power budget allocation in multi-processor system

Apparatus and method of balancing input power from multiple sources

Patents Applicationslast 30 patents

DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

Regional Adjustment of Render Rate

BARRIERS AND SYNCHRONIZATION FOR MACHINE LEARNING AT AUTONOMOUS MAC...

INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERAT...

Regional Adjustment of Render Rate

GRAPHICS PROCESSING UNIT PROCESSING AND CACHING IMPROVEMENTS

COORDINATION AND INCREASED UTILIZATION OF GRAPHICS PROCESSORS DURIN...

DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

DYNAMIC PRECISION FOR NEURAL NETWORK COMPUTE OPERATIONS

HYBRID LOW POWER HOMOGENOUS GRAPICS PROCESSING UNITS

DYNAMIC DISTRIBUTED TRAINING OF MACHINE LEARNING MODELS

GRAPHICS PROCESSING UNIT PROCESSING AND CACHING IMPROVEMENTS

Regional Adjustment of Render Rate

INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERAT...

DYNAMIC POWER BUDGET ALLOCATION IN MULTI-PROCESSOR SYSTEM

COORDINATION AND INCREASED UTILIZATION OF GRAPHICS PROCESSORS DURIN...

BARRIERS AND SYNCHRONIZATION FOR MACHINE LEARNING AT AUTONOMOUS MAC...

INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERAT...

SYSTEMS AND METHODS FOR CACHE OPTIMIZATION

EFFICIENT THREAD GROUP SCHEDULING

DATA OPERATIONS AND FINITE STATE MACHINE FOR MACHINE LEARNING VIA B...

HYBRID LOW POWER HOMOGENOUS GRAPICS PROCESSING UNITS

ENABLING PRODUCT SKUS BASED ON CHIPLET CONFIGURATIONS

DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

SYSTEMS AND METHODS FOR CACHE OPTIMIZATION

SYSTEMS AND METHODS FOR CACHE OPTIMIZATION

Regional Adjustment of Render Rate

ADAPTIVE MULTIBIT BUS FOR ENERGY OPTIMIZATION

DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE