SANTANU CHAUDHURI

Person

Mountain View, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Adaptive delay base loss equalization
- Patent number 9,219,623
- Issue date Dec 22, 2015
- Intel Corporation
- James A. McCall
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system of adapting communication links to link condition...
- Patent number 9,104,793
- Issue date Aug 11, 2015
- Intel Corporation
- Venkatraman Iyer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory link initialization
- Patent number 8,578,086
- Issue date Nov 5, 2013
- Intel Corporation
- Santanu Chaudhuri
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for training a memory signal via an error sign...
- Patent number 8,533,538
- Issue date Sep 10, 2013
- Intel Corporation
- Santanu Chaudhuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable passive equalizer
- Patent number 7,671,694
- Issue date Mar 2, 2010
- Intel Corporation
- Evelina F Yeung
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Local receive clock signal adjustment
- Patent number 7,478,257
- Issue date Jan 13, 2009
- Intel Corporation
- Sanjay Dabral
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable passive equalizer
- Patent number 7,394,331
- Issue date Jul 1, 2008
- Evelina F Yeung
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for periodically retraining a serial links int...
- Patent number 7,209,907
- Issue date Apr 24, 2007
- Intel Corporation
- Naveen Cherukuri
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low gain phase-locked loop circuit
- Patent number 6,977,537
- Issue date Dec 20, 2005
- Intel Corporation
- Santanu Chaudhuri
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Setting multiple chip parameters using one IC terminal
- Patent number 6,922,071
- Issue date Jul 26, 2005
- Intel Corporation
- Sanjay Dabral
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low gain phase-locked loop circuit
- Patent number 6,788,155
- Issue date Sep 7, 2004
- Intel Corporation
- Santanu Chaudhuri
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND SYSTEM OF REDUCING POWER SUPPLY NOISE DURING TRAINING OF...
- Publication number 20130279622
- Publication date Oct 24, 2013
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM OF ADAPTING COMMUNICATION LINKS TO LINK CONDITION...
- Publication number 20120079160
- Publication date Mar 29, 2012
- VENKATRAMAN IYER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR TRAINING A MEMORY SIGNAL VIA AN ERROR SIGN...
- Publication number 20110320867
- Publication date Dec 29, 2011
- Santanu Chaudhuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY LINK INITIALIZATION
- Publication number 20110078370
- Publication date Mar 31, 2011
- SANTANU CHAUDHURI
- G11 - INFORMATION STORAGE
Information Patent Application
Programmable passive equalizer
- Publication number 20080238588
- Publication date Oct 2, 2008
- Evelina F. Yeung
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Programmable passive equalizer
- Publication number 20070030092
- Publication date Feb 8, 2007
- Evelina F. Yeung
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Adaptive delay base loss equalization
- Publication number 20060067398
- Publication date Mar 30, 2006
- James A. McCall
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus for periodically retraining a serial links int...
- Publication number 20050286567
- Publication date Dec 29, 2005
- Naveen Cherukuri
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System and method for automatically calibrating two-tap and multi-t...
- Publication number 20050201454
- Publication date Sep 15, 2005
- Intel Corporation
- Santanu Chaudhuri
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Setting multiple chip parameters using one IC terminal
- Publication number 20050099219
- Publication date May 12, 2005
- Sanjay Dabral
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low gain phase-locked loop circuit
- Publication number 20040246057
- Publication date Dec 9, 2004
- Santanu Chaudhuri
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Local receive clock signal adjustment
- Publication number 20040226997
- Publication date Nov 18, 2004
- Sanjay Dabral
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Setting multiple chip parameters using one IC terminal
- Publication number 20040124875
- Publication date Jul 1, 2004
- Sanjay Dabral
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low gain phase-locked loop circuit
- Publication number 20040124884
- Publication date Jul 1, 2004
- Santanu Chaudhuri
- H03 - BASIC ELECTRONIC CIRCUITRY

SANTANU CHAUDHURI

Person

Patents Grantslast 30 patents

Adaptive delay base loss equalization

Method and system of adapting communication links to link condition...

Memory link initialization

Method and apparatus for training a memory signal via an error sign...

Programmable passive equalizer

Local receive clock signal adjustment

Programmable passive equalizer

Method and apparatus for periodically retraining a serial links int...

Low gain phase-locked loop circuit

Setting multiple chip parameters using one IC terminal

Low gain phase-locked loop circuit

Patents Applicationslast 30 patents

METHOD AND SYSTEM OF REDUCING POWER SUPPLY NOISE DURING TRAINING OF...

METHOD AND SYSTEM OF ADAPTING COMMUNICATION LINKS TO LINK CONDITION...

METHOD AND APPARATUS FOR TRAINING A MEMORY SIGNAL VIA AN ERROR SIGN...

MEMORY LINK INITIALIZATION

Programmable passive equalizer

Programmable passive equalizer

Adaptive delay base loss equalization

Method and apparatus for periodically retraining a serial links int...

System and method for automatically calibrating two-tap and multi-t...

Setting multiple chip parameters using one IC terminal

Low gain phase-locked loop circuit

Local receive clock signal adjustment

Setting multiple chip parameters using one IC terminal

Low gain phase-locked loop circuit