SAPUMAL WIJERATNE

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Fast dynamic capacitance, frequency, and/or voltage throttling appa...
- Patent number 11,275,663
- Issue date Mar 15, 2022
- Intel Corporation
- Alexander Gendler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Keeper circuit
- Patent number 8,362,806
- Issue date Jan 29, 2013
- Intel Corporation
- Sapumal B. Wijeratne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and system to lower the minimum operating voltage of registe...
- Patent number 8,320,203
- Issue date Nov 27, 2012
- Intel Corporation
- Seung H. Hwang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reducing leakage in bit lines of a memory...
- Patent number 7,952,941
- Issue date May 31, 2011
- Intel Corporation
- Sapumal B Wijeratne
- G11 - INFORMATION STORAGE
Information Patent Grant
Ultra low voltage, low leakage, high density, variation tolerant me...
- Patent number 7,656,702
- Issue date Feb 2, 2010
- Intel Corporation
- Sapumal Wijeratne
- G11 - INFORMATION STORAGE
Information Patent Grant
Carry-skip adder having merged carry-skip cells with sum cells
- Patent number 7,516,173
- Issue date Apr 7, 2009
- Intel Corporation
- Sapumal Wijeratne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse tree adder circuit
- Patent number 7,509,368
- Issue date Mar 24, 2009
- Intel Corporation
- Mark A. Anders
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder circuit with sense-amplifier multiplexer front-end
- Patent number 7,325,024
- Issue date Jan 29, 2008
- Intel Corporation
- Sanu K. Mathew
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single stage level restore circuit with hold functionality
- Patent number 7,202,703
- Issue date Apr 10, 2007
- Intel Corporation
- Sapumal Wijeratne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Ratioed logic circuits with contention interrupt
- Patent number 7,161,389
- Issue date Jan 9, 2007
- Intel Corporation
- Sapumal Wijeratne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Leakage tolerant register file
- Patent number 7,002,855
- Issue date Feb 21, 2006
- Intel Corporation
- Sapumal Wijeratne
- G11 - INFORMATION STORAGE
Information Patent Grant
Single stage, level restore circuit with mixed signal inputs
- Patent number 6,958,629
- Issue date Oct 25, 2005
- Intel Corporation
- Sapumal Wijeratne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Select logic for low voltage swing circuits
- Patent number 6,922,082
- Issue date Jul 26, 2005
- Intel Corporation
- Sapumal Wijeratne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for fully automated signal integrity analysis...
- Patent number 6,836,755
- Issue date Dec 28, 2004
- Intel Corporation
- Mark D. Nardin
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Apparatus and Method for Temperature-Constrained Frequency Control...
- Publication number 20240330234
- Publication date Oct 3, 2024
- Intel Corporation,
- Jianwei DAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST DYNAMIC CAPACITANCE, FREQUENCY, AND/OR VOLTAGE THROTTLING APPA...
- Publication number 20210382805
- Publication date Dec 9, 2021
- Intel Corporation
- Alexander Gendler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM TO LOWER THE MINIMUM OPERATING VOLTAGE OF REGISTE...
- Publication number 20110235445
- Publication date Sep 29, 2011
- Seung H. Hwang
- G11 - INFORMATION STORAGE
Information Patent Application
Keeper circuit
- Publication number 20100327909
- Publication date Dec 30, 2010
- Sapumal B. Wijeratne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND APPARATUS FOR REDUCING LEAKAGE IN BIT LINES OF A MEMORY...
- Publication number 20100165753
- Publication date Jul 1, 2010
- Sapumal B Wijeratne
- G11 - INFORMATION STORAGE
Information Patent Application
Ultra low voltage, low leakage, high density, variation tolerant me...
- Publication number 20090168509
- Publication date Jul 2, 2009
- Sapumal Wijeratne
- G11 - INFORMATION STORAGE
Information Patent Application
Methods and apparatuses for operating memory
- Publication number 20090086556
- Publication date Apr 2, 2009
- Sapumal Wijeratne
- G11 - INFORMATION STORAGE
Information Patent Application
Sparse tree adder circuit
- Publication number 20060253523
- Publication date Nov 9, 2006
- Intel Corporation
- Mark A. Anders
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Carry-skip adder having merged carry-skip cells with sum cells
- Publication number 20060031280
- Publication date Feb 9, 2006
- Sapumal Wijeratne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Ratioed logic circuits with contention interrupt
- Publication number 20060001452
- Publication date Jan 5, 2006
- Sapumal Wijeratne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Single stage level restore circuit with hold functionality
- Publication number 20050169074
- Publication date Aug 4, 2005
- Sapumal Wijeratne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SINGLE STAGE, LEVEL RESTORE CIRCUIT WITH MIXED SIGNAL INPUTS
- Publication number 20050168244
- Publication date Aug 4, 2005
- Sapumal Wijeratne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Adder circuit with sense-amplifier multiplexer front-end
- Publication number 20050125481
- Publication date Jun 9, 2005
- Sanu K. Mathew
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Leakage tolerant register file
- Publication number 20050068827
- Publication date Mar 31, 2005
- Sapumal Wijeratne
- G11 - INFORMATION STORAGE
Information Patent Application
SELECT LOGIC FOR LOW VOLTAGE SWING CIRCUITS
- Publication number 20050068065
- Publication date Mar 31, 2005
- Sapumal Wijeratne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND APPARATUS FOR FULLY AUTOMATED SIGNAL INTEGRITY ANALYSIS...
- Publication number 20030078764
- Publication date Apr 24, 2003
- MARK D. NARDIN
- G06 - COMPUTING CALCULATING COUNTING

SAPUMAL WIJERATNE

Person

Patents Grantslast 30 patents

Fast dynamic capacitance, frequency, and/or voltage throttling appa...

Keeper circuit

Method and system to lower the minimum operating voltage of registe...

Method and apparatus for reducing leakage in bit lines of a memory...

Ultra low voltage, low leakage, high density, variation tolerant me...

Carry-skip adder having merged carry-skip cells with sum cells

Sparse tree adder circuit

Adder circuit with sense-amplifier multiplexer front-end

Single stage level restore circuit with hold functionality

Ratioed logic circuits with contention interrupt

Leakage tolerant register file

Single stage, level restore circuit with mixed signal inputs

Select logic for low voltage swing circuits

Method and apparatus for fully automated signal integrity analysis...

Patents Applicationslast 30 patents

Apparatus and Method for Temperature-Constrained Frequency Control...

FAST DYNAMIC CAPACITANCE, FREQUENCY, AND/OR VOLTAGE THROTTLING APPA...

METHOD AND SYSTEM TO LOWER THE MINIMUM OPERATING VOLTAGE OF REGISTE...

Keeper circuit

METHOD AND APPARATUS FOR REDUCING LEAKAGE IN BIT LINES OF A MEMORY...

Ultra low voltage, low leakage, high density, variation tolerant me...

Methods and apparatuses for operating memory

Sparse tree adder circuit

Carry-skip adder having merged carry-skip cells with sum cells

Ratioed logic circuits with contention interrupt

Single stage level restore circuit with hold functionality

SINGLE STAGE, LEVEL RESTORE CIRCUIT WITH MIXED SIGNAL INPUTS

Adder circuit with sense-amplifier multiplexer front-end

Leakage tolerant register file

SELECT LOGIC FOR LOW VOLTAGE SWING CIRCUITS

METHOD AND APPARATUS FOR FULLY AUTOMATED SIGNAL INTEGRITY ANALYSIS...