Sarah H. Knickerbocker

Person

Hopewell Junction, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-layered substrates of semiconductor devices
- Patent number 11,502,106
- Issue date Nov 15, 2022
- GLOBALFOUNDRIES U.S. Inc.
- Benjamin Vito Fasano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fiber alignment to photonics chip
- Patent number 10,520,679
- Issue date Dec 31, 2019
- GLOBALFOUNDRIES Inc.
- Sarah Knickerbocker
- G02 - OPTICS
Information Patent Grant
Dicing channels for glass interposers
- Patent number 10,090,255
- Issue date Oct 2, 2018
- GLOBALFOUNDRIES Inc.
- Brittany L. Hedrick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual layer stack for contact formation
- Patent number 9,401,336
- Issue date Jul 26, 2016
- International Business Machines Corporation
- Charles L. Arvin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit assembly with cushion polymer layer
- Patent number 9,362,223
- Issue date Jun 7, 2016
- International Business Machines Corporation
- Paul S. Andry
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit assembly with cushion polymer layer
- Patent number 9,209,128
- Issue date Dec 8, 2015
- International Business Machines Corporation
- Paul S. Andry
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Handler wafer removal facilitated by the addition of an amorphous c...
- Patent number 9,171,749
- Issue date Oct 27, 2015
- GlobalFoundries U.S. 2 LLC
- Bing Dang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduction of edge chipping during wafer handling
- Patent number 8,807,184
- Issue date Aug 19, 2014
- International Business Machines Corporation
- Sarah H. Knickerbocker
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Reduction of edge chipping during wafer handling
- Patent number 8,753,460
- Issue date Jun 17, 2014
- International Business Machines Corporation
- Sarah H. Knickerbocker
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Protecting a mold having a substantially planar surface provided wi...
- Patent number 8,668,834
- Issue date Mar 11, 2014
- International Business Machines Corporations
- Bradley P. Jones
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and structure for optimizing yield of 3-D chip manufacture
- Patent number 7,999,377
- Issue date Aug 16, 2011
- International Business Machines Corporation
- Edward M. DeMulder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for making interconnect solder Pb-free bumps free from orga...
- Patent number 7,833,897
- Issue date Nov 16, 2010
- International Business Machines Corporation
- Sarah H. Knickerbocker
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Forming robust solder interconnect structures by reducing effects o...
- Patent number 7,767,575
- Issue date Aug 3, 2010
- Tessera Intellectual Properties, Inc.
- Kamalesh K. Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure for optimizing yield of 3-D chip manufacture
- Patent number 7,737,003
- Issue date Jun 15, 2010
- International Business Machines Corporation
- Edward M. DeMulder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Alignment verification for C4NP solder transfer
- Patent number 7,666,780
- Issue date Feb 23, 2010
- International Business Machines Corporation
- Jerry A. Gorrell
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of forming a bond pad on an I/C chip and resulting structure
- Patent number 7,572,726
- Issue date Aug 11, 2009
- International Business Machines Corporation
- Julie C. Biggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming robust solder interconnect structures by reducin...
- Patent number 7,473,997
- Issue date Jan 6, 2009
- International Business Machines Corporation
- Kamalesh K. Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for selective electroplating of semiconductor device I/O pad...
- Patent number 7,144,490
- Issue date Dec 5, 2006
- International Business Machines Corporation
- Tien-Jen Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming robust solder interconnect structures by reducin...
- Patent number 6,995,084
- Issue date Feb 7, 2006
- International Business Machines Corporation
- Kamalesh K. Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
I/C chip suitable for wire bonding
- Patent number 6,995,475
- Issue date Feb 7, 2006
- International Business Machines Corporation
- Julie C. Biggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low impedance power distribution structure for a semiconductor chip...
- Patent number 6,661,100
- Issue date Dec 9, 2003
- International Business Machines Corporation
- Brent A. Anderson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Baseplate for chip burn-in and/of testing, and method thereof
- Patent number 6,335,210
- Issue date Jan 1, 2002
- International Business Machines Corporation
- Mukta S. Farooq
- G01 - MEASURING TESTING
Information Patent Grant
Method of producing heat dissipating structure for semiconductor de...
- Patent number 6,284,574
- Issue date Sep 4, 2001
- International Business Machines Corporation
- Kevin Shawn Petrarca
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Universal cost reduced substrate structure method and apparatus
- Patent number 5,946,552
- Issue date Aug 31, 1999
- International Business Machines Corporation
- Kenneth Alfred Bird
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic component package with decoupling capacitors completely...
- Patent number 5,831,810
- Issue date Nov 3, 1998
- International Business Machines Corporation
- Kenneth A. Bird
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Large ceramic article and method of manufacturing
- Patent number 5,541,005
- Issue date Jul 30, 1996
- International Business Machines Corporation
- Raschid J. Bezama
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for producing ceramic circuit structures having conductive...
- Patent number 5,337,475
- Issue date Aug 16, 1994
- International Business Machines Corporation
- Farid Y. Aoude
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via paste compositions and use thereof to form conductive vias in c...
- Patent number 5,283,104
- Issue date Feb 1, 1994
- International Business Machines Corporation
- Farid Y. Aoude
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating a low dielectric composite substrate
- Patent number 5,277,725
- Issue date Jan 11, 1994
- International Business Machines Corporation
- John Acocella
- C04 - CEMENTS CONCRETE ARTIFICIAL STONE CERAMICS REFRACTORIES
Information Patent Grant
Zirconia toughening of glass-ceramic materials
- Patent number 5,185,215
- Issue date Feb 9, 1993
- International Business Machines Corporation
- Richard W. Adams
- C04 - CEMENTS CONCRETE ARTIFICIAL STONE CERAMICS REFRACTORIES

Patents Applicationslast 30 patents

Information Patent Application
BONDING STRUCTURE USING TWO OXIDE LAYERS WITH DIFFERENT STRESS LEVE...
- Publication number 20240079360
- Publication date Mar 7, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Jorge A. Lubguban
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-LAYERED SUBSTRATES OF SEMICONDUCTOR DEVICES
- Publication number 20210249442
- Publication date Aug 12, 2021
- GLOBALFOUNDRIES U.S. Inc.
- BENJAMIN VITO FASANO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURES AND METHODS FOR ALIGNING AND SECURING OPTICAL FIBERS IN...
- Publication number 20210173145
- Publication date Jun 10, 2021
- GLOBALFOUNDRIES U.S. Inc.
- Benjamin V. Fasano
- G02 - OPTICS
Information Patent Application
Fiber Alignment to Photonics Chip
- Publication number 20190369339
- Publication date Dec 5, 2019
- GLOBALFOUNDRIES INC.
- Sarah Knickerbocker
- G02 - OPTICS
Information Patent Application
DICING CHANNELS FOR GLASS INTERPOSERS
- Publication number 20170221837
- Publication date Aug 3, 2017
- GLOBALFOUNDRIES Inc.
- Brittany L. Hedrick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL LAYER STACK FOR CONTACT FORMATION
- Publication number 20160126201
- Publication date May 5, 2016
- International Business Machines Corporation
- Charles L. Arvin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT ASSEMBLY WITH CUSHION POLYMER LAYER
- Publication number 20150357283
- Publication date Dec 10, 2015
- International Business Machines Corporation
- Paul S. Andry
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT ASSEMBLY WITH CUSHION POLYMER LAYER
- Publication number 20150279779
- Publication date Oct 1, 2015
- Hitachi Chemical DuPont Microsystems, L.L.C.
- Paul S. Andry
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HANDLER WAFER REMOVAL
- Publication number 20150132924
- Publication date May 14, 2015
- International Business Machines Corporation
- Bing Dang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIXTURE PLANARITY EVALUATION METHOD
- Publication number 20140192341
- Publication date Jul 10, 2014
- International Business Machines Corporation
- Sarah H. Knickerbocker
- G01 - MEASURING TESTING
Information Patent Application
REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING
- Publication number 20130164912
- Publication date Jun 27, 2013
- International Business Machines Corporation
- Sarah H. Knickerbocker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING
- Publication number 20130160705
- Publication date Jun 27, 2013
- International Business Machines Corporation
- Sarah H. Knickerbocker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROTECTING A MOLD HAVING A SUBSTANTIALLY PLANAR SURFACE PROVIDED WI...
- Publication number 20120207920
- Publication date Aug 16, 2012
- International Business Machines Corporation
- Bradley P. Jones
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING
- Publication number 20120193014
- Publication date Aug 2, 2012
- International Business Machines Corporation
- SARAH H. KNICKERBOCKER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING A PROTECTIVE LAYER ON A MOLD AND MOLD HAVING A PROTECTIVE L...
- Publication number 20110079702
- Publication date Apr 7, 2011
- International Business Machines Corporation
- Bradley P. Jones
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
ALIGNMENT VERIFICATION FOR C4NP SOLDER TRANSFER
- Publication number 20090181533
- Publication date Jul 16, 2009
- International Business Machines Corporation
- Jerry A. Gorrell
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCING EFFECTS O...
- Publication number 20090163019
- Publication date Jun 25, 2009
- International Business Machines Corporation
- Kamalesh K. Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR MAKING INTERCONNECT SOLDER Pb-FREE BUMPS FREE FROM ORGA...
- Publication number 20090020590
- Publication date Jan 22, 2009
- International Business Machines Corporation
- Sarah H. Knickerbocker
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method and Structure for Optimizing Yield of 3-D Chip Manufacture
- Publication number 20080142959
- Publication date Jun 19, 2008
- Edward M. DeMulder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND STRUCTURE FOR OPTIMIZING YIELD OF 3-D CHIP MANUFACTURE
- Publication number 20070080448
- Publication date Apr 12, 2007
- International Business Machines Corporation
- Edward M. DeMulder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Device with area array pads for test probing
- Publication number 20060249854
- Publication date Nov 9, 2006
- Tien-Jen Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming a bond pad on an I/C chip and resulting structure
- Publication number 20060081981
- Publication date Apr 20, 2006
- International Business Machines Corporation
- Julie C. Biggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCIN...
- Publication number 20060009022
- Publication date Jan 12, 2006
- International Business Machines Corporation
- Kamalesh K. Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCIN...
- Publication number 20050208748
- Publication date Sep 22, 2005
- International Business Machines Corporation
- Kamalesh K. Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE WITH AREA ARRAY PADS FOR TEST PROBING
- Publication number 20050167837
- Publication date Aug 4, 2005
- International Business Machines Corporation
- Tien-Jen Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR SELECTIVE ELECTROPLATING OF SEMICONDUCTOR DEVICE I/O PAD...
- Publication number 20050103636
- Publication date May 19, 2005
- International Business Machines Corporation
- Tien-Jen Cheng
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
Method of forming a bond pad on an I/C chip and resulting structure
- Publication number 20050062170
- Publication date Mar 24, 2005
- International Business Machines Corporation
- Julie C. Biggs
- H01 - BASIC ELECTRIC ELEMENTS

Sarah H. Knickerbocker

Person

Patents Grantslast 30 patents

Multi-layered substrates of semiconductor devices

Fiber alignment to photonics chip

Dicing channels for glass interposers

Dual layer stack for contact formation

Integrated circuit assembly with cushion polymer layer

Integrated circuit assembly with cushion polymer layer

Handler wafer removal facilitated by the addition of an amorphous c...

Reduction of edge chipping during wafer handling

Reduction of edge chipping during wafer handling

Protecting a mold having a substantially planar surface provided wi...

Method and structure for optimizing yield of 3-D chip manufacture

Process for making interconnect solder Pb-free bumps free from orga...

Forming robust solder interconnect structures by reducing effects o...

Method and structure for optimizing yield of 3-D chip manufacture

Alignment verification for C4NP solder transfer

Method of forming a bond pad on an I/C chip and resulting structure

Method for forming robust solder interconnect structures by reducin...

Method for selective electroplating of semiconductor device I/O pad...

Method for forming robust solder interconnect structures by reducin...

I/C chip suitable for wire bonding

Low impedance power distribution structure for a semiconductor chip...

Baseplate for chip burn-in and/of testing, and method thereof

Method of producing heat dissipating structure for semiconductor de...

Universal cost reduced substrate structure method and apparatus

Electronic component package with decoupling capacitors completely...

Large ceramic article and method of manufacturing

Process for producing ceramic circuit structures having conductive...

Via paste compositions and use thereof to form conductive vias in c...

Process for fabricating a low dielectric composite substrate

Zirconia toughening of glass-ceramic materials

Patents Applicationslast 30 patents

BONDING STRUCTURE USING TWO OXIDE LAYERS WITH DIFFERENT STRESS LEVE...

MULTI-LAYERED SUBSTRATES OF SEMICONDUCTOR DEVICES

STRUCTURES AND METHODS FOR ALIGNING AND SECURING OPTICAL FIBERS IN...

Fiber Alignment to Photonics Chip

DICING CHANNELS FOR GLASS INTERPOSERS

DUAL LAYER STACK FOR CONTACT FORMATION

INTEGRATED CIRCUIT ASSEMBLY WITH CUSHION POLYMER LAYER

INTEGRATED CIRCUIT ASSEMBLY WITH CUSHION POLYMER LAYER

HANDLER WAFER REMOVAL

FIXTURE PLANARITY EVALUATION METHOD

REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING

REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING

PROTECTING A MOLD HAVING A SUBSTANTIALLY PLANAR SURFACE PROVIDED WI...

REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING

FORMING A PROTECTIVE LAYER ON A MOLD AND MOLD HAVING A PROTECTIVE L...

ALIGNMENT VERIFICATION FOR C4NP SOLDER TRANSFER

FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCING EFFECTS O...

PROCESS FOR MAKING INTERCONNECT SOLDER Pb-FREE BUMPS FREE FROM ORGA...

Method and Structure for Optimizing Yield of 3-D Chip Manufacture

METHOD AND STRUCTURE FOR OPTIMIZING YIELD OF 3-D CHIP MANUFACTURE

Device with area array pads for test probing

Method of forming a bond pad on an I/C chip and resulting structure

METHOD FOR FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCIN...

METHOD FOR FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCIN...

DEVICE WITH AREA ARRAY PADS FOR TEST PROBING

METHOD FOR SELECTIVE ELECTROPLATING OF SEMICONDUCTOR DEVICE I/O PAD...

Method of forming a bond pad on an I/C chip and resulting structure