Sarma Vrudhula

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Threshold logic gates using flash transistors
- Patent number 12,057,831
- Issue date Aug 6, 2024
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- G11 - INFORMATION STORAGE
Information Patent Grant
Neural network circuitry having approximate multiplier units
- Patent number 11,599,779
- Issue date Mar 7, 2023
- Arizona Board of Regents on behalf of Arizona State University
- Elham Azari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA with reconfigurable threshold logic gates for improved perform...
- Patent number 11,356,100
- Issue date Jun 7, 2022
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile logic device for energy-efficient logic state restoration
- Patent number 10,795,809
- Issue date Oct 6, 2020
- Arizona Board of Regents on behalf of Arizona State University
- Jinghua Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock skewing strategy to reduce dynamic power and eliminate hold-t...
- Patent number 10,551,869
- Issue date Feb 4, 2020
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hold violation free scan chain and scanning mechanism for testing o...
- Patent number 10,447,249
- Issue date Oct 15, 2019
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Energy efficient, robust differential mode d-flip-flop
- Patent number 10,250,236
- Issue date Apr 2, 2019
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Processor control system
- Patent number 10,133,323
- Issue date Nov 20, 2018
- Arizona Board of Regents for and on behalf of Arizona State University
- Vinay Hanumaiah
- G05 - CONTROLLING REGULATING
Information Patent Grant
Neuromorphic computational system(s) using resistive synaptic devices
- Patent number 9,934,463
- Issue date Apr 3, 2018
- Arizona Board of Regents on behalf of Arizona State University
- Jae-sun Seo
- G11 - INFORMATION STORAGE
Information Patent Grant
Determining parameters that affect processor energy efficiency
- Patent number 9,933,825
- Issue date Apr 3, 2018
- Arizona Board of Regents for and on behalf of Arizona State University
- Vinay Hanumaiah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of obfuscating digital logic circuits using threshold voltage
- Patent number 9,876,503
- Issue date Jan 23, 2018
- Arixona Board of Regents on Behalf of Arizona State University
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Robust, low power, reconfigurable threshold logic array
- Patent number 9,490,815
- Issue date Nov 8, 2016
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Threshold logic element with stabilizing feedback
- Patent number 9,473,139
- Issue date Oct 18, 2016
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistive cross-point architecture for robust data representation w...
- Patent number 9,466,362
- Issue date Oct 11, 2016
- Arizona Board of Regents on behalf of Arizona State University
- Shimeng Yu
- G11 - INFORMATION STORAGE
Information Patent Grant
Threshold logic gates with resistive networks
- Patent number 9,356,598
- Issue date May 31, 2016
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- G11 - INFORMATION STORAGE
Information Patent Grant
Threshold gate and threshold logic array
- Patent number 9,306,151
- Issue date Apr 5, 2016
- Arizona Board of Regents, a body corporate of the State of Arizona, acting fo...
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Technology mapping for threshold and logic gate hybrid circuits
- Patent number 8,832,614
- Issue date Sep 9, 2014
- Arizona Board of Regents, a body corporate of the State of Arizona, acting fo...
- Sarma Vrudhula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decomposition based approach for the synthesis of threshold logic c...
- Patent number 8,601,417
- Issue date Dec 3, 2013
- Arizona Board of Regents for and on behalf of Arizona State University
- Tejaswi Gowda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combinational equivalence checking for threshold logic circuits
- Patent number 8,181,133
- Issue date May 15, 2012
- Arizona Board of Regents for and on behalf of Arizona State University
- Tejaswi Gowda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Threshold logic element having low leakage power and high performance
- Patent number 8,164,359
- Issue date Apr 24, 2012
- Arizona Board of Regents for and on behalf of Arizona State University
- Samuel Leshner
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of evaluating integrated circuit system performance using or...
- Patent number 7,630,852
- Issue date Dec 8, 2009
- Arizona Board of Regents
- Praveen Ghanta
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
COMPUTING IN MEMORY WITH ARTIFICIAL NEURONS
- Publication number 20230385624
- Publication date Nov 30, 2023
- Arizona Board of Regents on behalf of Arizona State University
- Sarma VRUDHULA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THRESHOLD LOGIC GATES USING FLASH TRANSISTORS
- Publication number 20220263508
- Publication date Aug 18, 2022
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURABLE BNN ASIC USING A NETWORK OF PROGRAMMABLE THRESHOLD LOG...
- Publication number 20220121915
- Publication date Apr 21, 2022
- Arizona Board of Regents on behalf of Arizona State University
- Ankit Wagle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FPGA WITH RECONFIGURABLE THRESHOLD LOGIC GATES FOR IMPROVED PERFORM...
- Publication number 20210013886
- Publication date Jan 14, 2021
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEURAL NETWORK CIRCUITRY
- Publication number 20200160159
- Publication date May 21, 2020
- Arizona Board of Regents on behalf of Arizona State University
- Elham Azari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-VOLATILE LOGIC DEVICE FOR ENERGY-EFFICIENT LOGIC STATE RESTORATION
- Publication number 20190213119
- Publication date Jul 11, 2019
- Arizona Board of Regents on behalf of Arizona State University
- Jinghua Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTROCARDIOGRAPHIC BIOMETRIC AUTHENTICATION
- Publication number 20190150794
- Publication date May 23, 2019
- Sarma Vrudhula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENERGY EFFICIENT, ROBUST DIFFERENTIAL MODE D-FLIP-FLOP
- Publication number 20180159512
- Publication date Jun 7, 2018
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HOLD VIOLATION FREE SCAN CHAIN AND SCANNING MECHANISM FOR TESTING O...
- Publication number 20180102766
- Publication date Apr 12, 2018
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- G01 - MEASURING TESTING
Information Patent Application
CLOCK SKEWING STRATEGY TO REDUCE DYNAMIC POWER AND ELIMINATE HOLD-T...
- Publication number 20170248989
- Publication date Aug 31, 2017
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF OBFUSCATING DIGITAL LOGIC CIRCUITS USING THRESHOLD VOLTAGE
- Publication number 20170187382
- Publication date Jun 29, 2017
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
NEUROMORPHIC COMPUTATIONAL SYSTEM(S) USING RESISTIVE SYNAPTIC DEVICES
- Publication number 20160336064
- Publication date Nov 17, 2016
- Arizona Board of Regents on behalf of Arizona State University
- Jae-sun Seo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROBUST, LOW POWER, RECONFIGURABLE THRESHOLD LOGIC ARRAY
- Publication number 20160164526
- Publication date Jun 9, 2016
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RESISTIVE CROSS-POINT ARCHITECTURE FOR ROBUST DATA REPRESENTATION W...
- Publication number 20160049195
- Publication date Feb 18, 2016
- Arizona Board of Regents on behalf of Arizona State University
- Shimeng Yu
- G11 - INFORMATION STORAGE
Information Patent Application
THRESHOLD LOGIC ELEMENT WITH STABILIZING FEEDBACK
- Publication number 20160006438
- Publication date Jan 7, 2016
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
THRESHOLD LOGIC GATES WITH RESISTIVE NETWORKS
- Publication number 20160006437
- Publication date Jan 7, 2016
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- G11 - INFORMATION STORAGE
Information Patent Application
DETERMINING PARAMETERS THAT AFFECT PROCESSOR ENERGY EFFICIENCY
- Publication number 20140281609
- Publication date Sep 18, 2014
- Arizona Board of Regents for and on behalf of Arizona State University
- Vinay Hanumaiah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR CONTROL SYSTEM
- Publication number 20140277815
- Publication date Sep 18, 2014
- Arizona Board of Regents for and on behalf of Arizona State University
- Vinay Hanumaiah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGY MAPPING FOR THRESHOLD AND LOGIC GATE HYBRID CIRCUITS
- Publication number 20130339914
- Publication date Dec 19, 2013
- Arizona Board of Regents, a body Corporate of the State of Arizona, Acting fo...
- Sarma Vrudhula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THRESHOLD GATE AND THRESHOLD LOGIC ARRAY
- Publication number 20130313623
- Publication date Nov 28, 2013
- Arizona Board of Regents, a body Corporate of the State of Arizona, Acting fo...
- Sarma Vrudhula
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DECOMPOSITION BASED APPROACH FOR THE SYNTHESIS OF THRESHOLD LOGIC C...
- Publication number 20110214095
- Publication date Sep 1, 2011
- Arizona Board of Regents for and on behalf of Arizona State University
- Tejaswi Gowda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THRESHOLD LOGIC ELEMENT HAVING LOW LEAKAGE POWER AND HIGH PERFORMANCE
- Publication number 20100321061
- Publication date Dec 23, 2010
- Arizona Board of Regents for and on behalf of Ariz ona State University
- Samuel Leshner
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Combinational Equivalence Checking for Threshold Logic Circuits
- Publication number 20090235216
- Publication date Sep 17, 2009
- Arizona Board of Regents, a body Corporate of the State of Arizona, Acting fo...
- Tejaswi Gowda
- G06 - COMPUTING CALCULATING COUNTING

Sarma Vrudhula

Person

Patents Grantslast 30 patents

Threshold logic gates using flash transistors

Neural network circuitry having approximate multiplier units

FPGA with reconfigurable threshold logic gates for improved perform...

Non-volatile logic device for energy-efficient logic state restoration

Clock skewing strategy to reduce dynamic power and eliminate hold-t...

Hold violation free scan chain and scanning mechanism for testing o...

Energy efficient, robust differential mode d-flip-flop

Processor control system

Neuromorphic computational system(s) using resistive synaptic devices

Determining parameters that affect processor energy efficiency

Method of obfuscating digital logic circuits using threshold voltage

Robust, low power, reconfigurable threshold logic array

Threshold logic element with stabilizing feedback

Resistive cross-point architecture for robust data representation w...

Threshold logic gates with resistive networks

Threshold gate and threshold logic array

Technology mapping for threshold and logic gate hybrid circuits

Decomposition based approach for the synthesis of threshold logic c...

Combinational equivalence checking for threshold logic circuits

Threshold logic element having low leakage power and high performance

Method of evaluating integrated circuit system performance using or...

Patents Applicationslast 30 patents

COMPUTING IN MEMORY WITH ARTIFICIAL NEURONS

THRESHOLD LOGIC GATES USING FLASH TRANSISTORS

CONFIGURABLE BNN ASIC USING A NETWORK OF PROGRAMMABLE THRESHOLD LOG...

FPGA WITH RECONFIGURABLE THRESHOLD LOGIC GATES FOR IMPROVED PERFORM...

NEURAL NETWORK CIRCUITRY

NON-VOLATILE LOGIC DEVICE FOR ENERGY-EFFICIENT LOGIC STATE RESTORATION

ELECTROCARDIOGRAPHIC BIOMETRIC AUTHENTICATION

ENERGY EFFICIENT, ROBUST DIFFERENTIAL MODE D-FLIP-FLOP

HOLD VIOLATION FREE SCAN CHAIN AND SCANNING MECHANISM FOR TESTING O...

CLOCK SKEWING STRATEGY TO REDUCE DYNAMIC POWER AND ELIMINATE HOLD-T...

METHOD OF OBFUSCATING DIGITAL LOGIC CIRCUITS USING THRESHOLD VOLTAGE

NEUROMORPHIC COMPUTATIONAL SYSTEM(S) USING RESISTIVE SYNAPTIC DEVICES

ROBUST, LOW POWER, RECONFIGURABLE THRESHOLD LOGIC ARRAY

RESISTIVE CROSS-POINT ARCHITECTURE FOR ROBUST DATA REPRESENTATION W...

THRESHOLD LOGIC ELEMENT WITH STABILIZING FEEDBACK

THRESHOLD LOGIC GATES WITH RESISTIVE NETWORKS

DETERMINING PARAMETERS THAT AFFECT PROCESSOR ENERGY EFFICIENCY

PROCESSOR CONTROL SYSTEM

TECHNOLOGY MAPPING FOR THRESHOLD AND LOGIC GATE HYBRID CIRCUITS

THRESHOLD GATE AND THRESHOLD LOGIC ARRAY

DECOMPOSITION BASED APPROACH FOR THE SYNTHESIS OF THRESHOLD LOGIC C...

THRESHOLD LOGIC ELEMENT HAVING LOW LEAKAGE POWER AND HIGH PERFORMANCE

Combinational Equivalence Checking for Threshold Logic Circuits