Sathya Narasimman Tiagaraj

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dual loop voltage regulator
- Patent number 12,164,319
- Issue date Dec 10, 2024
- Intel Corporation
- Sathya Narasimman Tiagaraj
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PACKAGE ARCHITECTURE OF LARGE DIES USING QUASI-MONOLITHIC CHIP LAYERS
- Publication number 20240063132
- Publication date Feb 22, 2024
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE DIMENSIONAL UNIVERSAL CHIPLET INTERCONNECT AS ON-PACKAGE INTE...
- Publication number 20240030172
- Publication date Jan 25, 2024
- Intel Corporation
- Debendra Das Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC DIE INCLUDING SWAPPABLE PHY CIRCUITRY AND SEMICONDU...
- Publication number 20230230923
- Publication date Jul 20, 2023
- Intel Corporation
- Gerald Pasdast
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER DELIVERY THROUGH CAPACITOR-DIES IN A MULTI-LAYERED MICROELECT...
- Publication number 20230163098
- Publication date May 25, 2023
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SKIP LEVEL VIAS IN METALLIZATION LAYERS FOR INTEGRATED CIRCUIT DEVICES
- Publication number 20230130935
- Publication date Apr 27, 2023
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PHYSICAL AND ELECTRICAL PROTOCOL TRANSLATION CHIPLETS
- Publication number 20230100228
- Publication date Mar 30, 2023
- Intel Corporation
- Gerald PASDAST
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REPAIR AND PERFORMANCE CHIPLET
- Publication number 20230100375
- Publication date Mar 30, 2023
- Intel Corporation
- Gerald PASDAST
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TEST AND DEBUG SUPPORT WITH HBI CHIPLET ARCHITECTURE
- Publication number 20230095914
- Publication date Mar 30, 2023
- Intel Corporation
- Gerald PASDAST
- G01 - MEASURING TESTING
Information Patent Application
SELECTIVE ROUTING THROUGH INTRA-CONNECT BRIDGE DIES
- Publication number 20220399277
- Publication date Dec 15, 2022
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ACTIVE DEVICE LAYER AT INTERCONNECT INTERFACES
- Publication number 20220399324
- Publication date Dec 15, 2022
- Intel Corporation
- Han Wui Then
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL LOOP VOLTAGE REGULATOR
- Publication number 20220197321
- Publication date Jun 23, 2022
- Intel Corporation
- Sathya Narasimman Tiagaraj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SKIP LEVEL VIAS IN METALLIZATION LAYERS FOR INTEGRATED CIRCUIT DEVICES
- Publication number 20210202377
- Publication date Jul 1, 2021
- Intel Corporation
- Adel Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS

Sathya Narasimman Tiagaraj

Person

Patents Grantslast 30 patents

Dual loop voltage regulator

Patents Applicationslast 30 patents

PACKAGE ARCHITECTURE OF LARGE DIES USING QUASI-MONOLITHIC CHIP LAYERS

THREE DIMENSIONAL UNIVERSAL CHIPLET INTERCONNECT AS ON-PACKAGE INTE...

MICROELECTRONIC DIE INCLUDING SWAPPABLE PHY CIRCUITRY AND SEMICONDU...

POWER DELIVERY THROUGH CAPACITOR-DIES IN A MULTI-LAYERED MICROELECT...

SKIP LEVEL VIAS IN METALLIZATION LAYERS FOR INTEGRATED CIRCUIT DEVICES

PHYSICAL AND ELECTRICAL PROTOCOL TRANSLATION CHIPLETS

REPAIR AND PERFORMANCE CHIPLET

TEST AND DEBUG SUPPORT WITH HBI CHIPLET ARCHITECTURE

SELECTIVE ROUTING THROUGH INTRA-CONNECT BRIDGE DIES

ACTIVE DEVICE LAYER AT INTERCONNECT INTERFACES

DUAL LOOP VOLTAGE REGULATOR

SKIP LEVEL VIAS IN METALLIZATION LAYERS FOR INTEGRATED CIRCUIT DEVICES