Satoshi Fujino

Follow

Person

Kanagawa, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Digital phase-locked loop
- Patent number 7,990,191
- Issue date Aug 2, 2011
- Renesas Electronics Corporation
- Satoshi Fujino
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Voltage-controlled oscillator including plurality of delay cells
- Patent number 7,911,282
- Issue date Mar 22, 2011
- Renesas Electronics Corporation
- Satoshi Fujino
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pulse width modulation circuit with multiphase clock
- Patent number 7,554,373
- Issue date Jun 30, 2009
- NEC Electronics Corporation
- Satoshi Fujino
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
MULTI-PHASE CLOCK GENERATION CIRCUIT
- Publication number 20110050312
- Publication date Mar 3, 2011
- NEC Electronics Corporation
- Satoshi Fujino
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Digital phase-locked loop
- Publication number 20100182060
- Publication date Jul 22, 2010
- NEC Electronics Corporation
- Satoshi Fujino
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Voltage-controlled oscillator including plurality of delay cells
- Publication number 20090261909
- Publication date Oct 22, 2009
- NEC Electronics Corporation
- Satoshi Fujino
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLL circuit including voltage controlled oscillator having voltage-...
- Publication number 20090189650
- Publication date Jul 30, 2009
- NEC Electronics Corporation
- Satoshi Fujino
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Pulse width modulation circuit
- Publication number 20060001467
- Publication date Jan 5, 2006
- NEC Electronics Corporation
- Satoshi Fujino
- H03 - BASIC ELECTRONIC CIRCUITRY