Satyamurthy Pullela

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Austin, TX, US

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Patents Grantslast 30 patents

Information Patent Grant
Optimizing combinational circuit layout through iterative restructu...
- Patent number 6,074,429
- Issue date Jun 13, 2000
- Motorola, Inc.
- Satyamurthy Pullela
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for optimizing element sizes in a semiconductor device
- Patent number 5,903,471
- Issue date May 11, 1999
- Motorola, Inc.
- Satyamurthy Pullela
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Complementary network reduction for load modeling
- Patent number 5,790,415
- Issue date Aug 4, 1998
- Satyamurthy Pullela
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simulation corrected sensitivity
- Patent number 5,787,008
- Issue date Jul 28, 1998
- Motorola, Inc.
- Satyamurthy Pullela
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accurate delay prediction based on multi-model analysis
- Patent number 5,751,593
- Issue date May 12, 1998
- Motorola, Inc.
- Satyamurthy Pullela
- G06 - COMPUTING CALCULATING COUNTING