Scott A. Johannesmeyer

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Richardson, TX, US

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Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit with scribe lane patterns for defect reduction
- Patent number 11,094,644
- Issue date Aug 17, 2021
- Texas Instruments Incorporated
- Adrian Salinas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of preventing seam defects in isolated lines
- Patent number 6,709,974
- Issue date Mar 23, 2004
- Texas Instruments Incorporated
- David Permana
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for processing a transistor channel layout
- Patent number 6,668,366
- Issue date Dec 23, 2003
- Texas Instruments Incorporated
- Hongmei Liao
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT WITH SCRIBE LANE PATTERNS FOR DEFECT REDUCTION
- Publication number 20210398910
- Publication date Dec 23, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Adrian SALINAS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT WITH SCRIBE LANE PATTERNS FOR DEFECT REDUCTION
- Publication number 20210104468
- Publication date Apr 8, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Adrian SALINAS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of preventing seam defects in isolated lines
- Publication number 20030199150
- Publication date Oct 23, 2003
- David Permana
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System and method for processing a transistor channel layout
- Publication number 20020023254
- Publication date Feb 21, 2002
- Hongmei Liao
- G06 - COMPUTING CALCULATING COUNTING