Scott A. Segan

Person

South Whitehall Township, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Adaptive voltage scaling using a serial interface
- Patent number 9,158,359
- Issue date Oct 13, 2015
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Michael S. Buonpane
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Integrated circuit power grid with improved routing resources and b...
- Patent number 9,070,684
- Issue date Jun 30, 2015
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Scott A. Segan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Critical-path circuit for performance monitoring
- Patent number 8,773,160
- Issue date Jul 8, 2014
- Agere Systems LLC
- James D. Chlipala
- G01 - MEASURING TESTING
Information Patent Grant
Delay circuit having reduced duty cycle distortion
- Patent number 8,680,907
- Issue date Mar 25, 2014
- Agere Systems LLC
- James D. Chlipala
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Critical-path circuit for performance monitoring
- Patent number 8,350,589
- Issue date Jan 8, 2013
- Agere Systems LLC
- James D. Chlipala
- G01 - MEASURING TESTING
Information Patent Grant
On-chip variation, speed and power regulator
- Patent number 8,315,830
- Issue date Nov 20, 2012
- Agere Systems LLC
- Richard P. Martin
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Integrated circuit performance enhancement using on-chip adaptive v...
- Patent number 8,161,431
- Issue date Apr 17, 2012
- Agere Systems Inc.
- Michael S. Buonpane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for deriving an integrated circuit (IC) clock...
- Patent number 7,786,814
- Issue date Aug 31, 2010
- Agere Systems Inc.
- Michael S. Buonpane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor device with variable pin locations
- Patent number 6,833,286
- Issue date Dec 21, 2004
- Agere Systems, INC
- Frederick H. Fischer
- G11 - INFORMATION STORAGE
Information Patent Grant
On-chip debugger
- Patent number 6,732,311
- Issue date May 4, 2004
- Agere Systems Inc.
- Frederick Harrison Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive bus arbitration using history buffer
- Patent number 6,513,082
- Issue date Jan 28, 2003
- Agere Systems Inc.
- Fredrick Harrison Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device with variable pin locations
- Patent number 6,465,884
- Issue date Oct 15, 2002
- Agere Systems Guardian Corp.
- Frederick H. Fischer
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory aliasing method and apparatus
- Patent number 6,438,672
- Issue date Aug 20, 2002
- Agere Systems Guardian Corp.
- Frederick Harrison Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frequency doubling method and apparatus
- Patent number 6,091,271
- Issue date Jul 18, 2000
- Lucent Technologies, Inc.
- Sandeep Pant
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fast transient circuit simulation of electronic circuits including...
- Patent number 6,023,576
- Issue date Feb 8, 2000
- Lucent Technologies Inc.
- Scott A. Segan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive addressable circuit redundancy method and apparatus
- Patent number 6,011,733
- Issue date Jan 4, 2000
- Lucent Technologies Inc.
- Frederick Harrison Fischer
- G11 - INFORMATION STORAGE
Information Patent Grant
Edge signal restoration circuit and method
- Patent number 5,945,850
- Issue date Aug 31, 1999
- Lucent Technologies Inc.
- Scott A. Segan
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHOD FOR SENSING TRANSISTOR MISMATCH
- Publication number 20140132303
- Publication date May 15, 2014
- LSI Corporation
- Scott A. Segan
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS AND METHOD FOR SENSING TRANSISTOR AGING EFFECTS
- Publication number 20140136128
- Publication date May 15, 2014
- LSI Corporation
- James D. Chlipala
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT POWER GRID WITH IMPROVED ROUTING RESOURCES AND B...
- Publication number 20130285219
- Publication date Oct 31, 2013
- LSI Corporation
- Scott A. Segan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Adaptive Voltage Scaling Using a Serial Interface
- Publication number 20130249290
- Publication date Sep 26, 2013
- LSI Corporation
- Michael S. Buonpane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CRITICAL-PATH CIRCUIT FOR PERFORMANCE MONITORING
- Publication number 20130088256
- Publication date Apr 11, 2013
- Agere Systems LLC
- James D. Chlipala
- G01 - MEASURING TESTING
Information Patent Application
CRITICAL-PATH CIRCUIT FOR PERFORMANCE MONITORING
- Publication number 20110267096
- Publication date Nov 3, 2011
- Agere Systems Inc.
- James D. Chlipala
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SECURE ELECTRICALLY PROGRAMMABLE FUSE AND METHOD OF OPERATING THE SAME
- Publication number 20110002186
- Publication date Jan 6, 2011
- LSI Corporation
- Michael S. Buonpane
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit Performance Enhancement Using On-Chip Adaptive V...
- Publication number 20100115475
- Publication date May 6, 2010
- Michael S. Buonpane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DERIVING AN INTEGRATED CIRCUIT (IC) CLOCK...
- Publication number 20100052800
- Publication date Mar 4, 2010
- Michael S. Buonpane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ON-CHIP VARIATION, SPEED AND POWER REGULATOR
- Publication number 20090177442
- Publication date Jul 9, 2009
- Agere Systems Inc.
- Richard P. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Delay Circuit Having Reduced Duty Cycle Distortion
- Publication number 20090108902
- Publication date Apr 30, 2009
- James D. Chlipala
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Adaptive Integrated Circuit Clock Skew Correction
- Publication number 20080129357
- Publication date Jun 5, 2008
- James D. Chlipala
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Semiconductor device with variable pin locations
- Publication number 20020190347
- Publication date Dec 19, 2002
- Frederick H. Fischer
- G11 - INFORMATION STORAGE

Scott A. Segan

Person

Patents Grantslast 30 patents

Adaptive voltage scaling using a serial interface

Integrated circuit power grid with improved routing resources and b...

Critical-path circuit for performance monitoring

Delay circuit having reduced duty cycle distortion

Critical-path circuit for performance monitoring

On-chip variation, speed and power regulator

Integrated circuit performance enhancement using on-chip adaptive v...

Method and apparatus for deriving an integrated circuit (IC) clock...

Semiconductor device with variable pin locations

On-chip debugger

Adaptive bus arbitration using history buffer

Semiconductor device with variable pin locations

Memory aliasing method and apparatus

Frequency doubling method and apparatus

Fast transient circuit simulation of electronic circuits including...

Adaptive addressable circuit redundancy method and apparatus

Edge signal restoration circuit and method

Patents Applicationslast 30 patents

APPARATUS AND METHOD FOR SENSING TRANSISTOR MISMATCH

APPARATUS AND METHOD FOR SENSING TRANSISTOR AGING EFFECTS

INTEGRATED CIRCUIT POWER GRID WITH IMPROVED ROUTING RESOURCES AND B...

Adaptive Voltage Scaling Using a Serial Interface

CRITICAL-PATH CIRCUIT FOR PERFORMANCE MONITORING

CRITICAL-PATH CIRCUIT FOR PERFORMANCE MONITORING

SECURE ELECTRICALLY PROGRAMMABLE FUSE AND METHOD OF OPERATING THE SAME

Integrated Circuit Performance Enhancement Using On-Chip Adaptive V...

METHOD AND APPARATUS FOR DERIVING AN INTEGRATED CIRCUIT (IC) CLOCK...

ON-CHIP VARIATION, SPEED AND POWER REGULATOR

Delay Circuit Having Reduced Duty Cycle Distortion

Adaptive Integrated Circuit Clock Skew Correction

Semiconductor device with variable pin locations