Patent Application
20140132303
Integrated circuits are often designed to incorporate various types of test circuitry. For example, it is well known to configure an integrated circuit to include scan test circuitry that facilitates testing for various internal fault conditions using applied test patterns. These internal fault conditions in many cases can be attributable at least in part to process-dependent differences in speed, drive strength or other characteristics between transistors of different conductivity types, such as n-type metal-oxide-semiconductor (NMOS) transistors and p-type metal-oxide-semiconductor (PMOS) transistors.
It is therefore often desirable to implement functionality for sensing transistor mismatch in an integrated circuit. For example, in conjunction with scan testing or other types of testing, transistor mismatch measurements may be useful in determining particular test patterns to apply, or in interpreting or otherwise processing test results. Additionally or alternatively, such measurements may be used in characterizing the ability of an integrated circuit to meet performance requirements under various environmental conditions, or in adjusting manufacturing processes to increase integrated circuit yield.
Unfortunately, conventional techniques generally fail to provide a sufficient level of accuracy and efficiency in the sensing of transistor mismatch. For example, such techniques may require the use of analog circuitry that is difficult to incorporate into an integrated circuit, or may consume excessive amounts of power within the integrated circuit. Also, the measurements generated by conventional techniques are typically not independent of voltage, temperature or clock frequency.
Embodiments of the invention provide improved transistor mismatch sensors that may be implemented within an integrated circuit and controlled, for example, by an external or internal tester.
In one embodiment, an integrated circuit implements a transistor mismatch sensor comprising first and second inverter chains coupled to a register. The register comprises a plurality of flip-flops having clock inputs driven by an output of the first inverter chain and data inputs driven by an output of the second inverter chain. Data outputs of the flip-flops of the register are indicative of an amount of mismatch between transistors of different conductivity types in the first and second inverter chains.
By way of example, the register may illustratively comprise a thermometer encoded register providing a digital output signal having a first value indicative of an approximate match in speed, drive strength or other characteristics between the transistors of the first and second conductivity types, with values above and below the first value being indicative of respective first and second different types of relative mismatch in speed, drive strength or other characteristics between the transistors of the first and second conductivity types.
The first and second inverter chains may each comprise an initial inverter and at least one additional inverter arranged in series with the initial inverter, with an output of the initial inverter being heavily loaded so as to exaggerate transition timing differences between the transistors of the different conductivity types in the corresponding inverter chains. For example, the output of the initial inverter in a given one of the first and second inverter chains may be heavily loaded by coupling that output to inputs of respective additional inverters each having a drive strength that is substantially larger than a drive strength of the initial inverter. As a more particular example, the drive strength of a given one of the additional inverters may be at least about 16 times the drive strength of the initial inverter.
The transition timing differences referred to above may illustratively be reflected in a difference between a pulse width from a rising edge to a falling edge in one of the first and second inverter chains and a pulse width from a falling edge to a rising edge in the other of the first and second inverter chains. In such an arrangement, this type of difference in transition timing between the first and second inverter chains is measured by the register to determine an amount of transistor mismatch.
One or more of the illustrative embodiments provide significant improvements relative to conventional practice. For example, a given such embodiment is implemented in the form of an all-digital transistor mismatch sensor in which measurements are substantially independent of voltage and temperature. Also, due to the self-timed configuration of the sensor, the measurements are substantially independent of clock frequency. Moreover, the transistor mismatch sensor is implemented so as to consume dynamic power only when making a measurement, and therefore without unduly increasing the power consumption of the corresponding integrated circuit.
Embodiments of the invention will be illustrated herein in conjunction with exemplary testing systems and associated integrated circuits comprising transistor mismatch sensors configured to determine mismatches in speed, drive strength or other characteristics between NMOS and PMOS transistors of the integrated circuits. It should be understood, however, that embodiments of the invention are more generally applicable to any testing system or associated integrated circuit in which it is desirable to provide sensing of transistor mismatch. Additional embodiments may be implemented using components other than those specifically shown and described in conjunction with the illustrative embodiments.
As will be described in greater detail below in conjunction with
The term “mismatch” as used herein is intended to be broadly construed so as to encompass, for example, differences in speed, drive strength or other transistor characteristics. Such differences may be attributable to process variations, temperature variations or other factors, in any combination.
Also, terms such as “driven” and “driving” are intended to encompass both direct and indirect driving arrangements. Thus, for example, in the case of an input driven by an output of an inverter chain, one or more circuitry elements may be arranged between the output and the input.
The additional circuitry 112 may comprise, for example, multiple integrated circuit cores, such as respective read channel and additional cores of a system-on-chip (SOC) integrated circuit in a hard disk drive (HDD) controller application, designed for reading and writing data from one or more magnetic storage disks of an HDD. In other embodiments, the additional circuitry 112 may comprise other types of functional logic circuitry, in any combination, and the term “additional circuitry” is intended to be broadly construed so as to cover any such arrangements of logic circuitry.
The particular configuration of testing system 100 as shown in
Referring now to
Portions of the tester 104 may be implemented at least in part in the form of software stored in memory 206 and executed by processor 204. For example, the memory 206 may store program code that is executed by the processor 204 to implement particular testing operations that utilize the transistor mismatch sensor 110 of integrated circuit 102. The memory 206 is an example of what is more generally referred to herein as a computer-readable medium or other type of computer program product having computer program code embodied therein, and may comprise, for example, electronic memory such as RAM or ROM, magnetic memory, optical memory, or other types of storage devices in any combination. The processor 204 may comprise a microprocessor, CPU, ASIC, FPGA or other type of processing device, as well as portions or combinations of such devices. Similar processor and memory elements may be used to implement at least a portion of the transistor mismatch sensor 110, as well as other portions of the integrated circuit 102.
It should be noted that the
The first inverter chain of the mismatch amplification circuitry 300 comprises inverters U1N and U2N and the second inverter chain comprises inverters U1P and U2P. The inverters U1N and U1P are the initial inverters of the respective inverter chains, and although each inverter chain in this embodiment comprises a series arrangement of two inverters, other embodiments may use series arrangements of more than two inverters to form the first and second inverter chains.
It should be noted that the circuits driving the inputs of the respective first and second inverter chains should generally have the same or similar drive strengths.
The output of the initial inverter in each of the first and second inverter chains is overloaded or otherwise heavily loaded in the present embodiment in order to exaggerate transition timing differences between transistors of different conductivity types in the corresponding inverter chain. The transition timing differences may be reflected in a difference between a pulse width from a rising edge to a falling edge in one of the first and second inverter chains and a pulse width from a falling edge to a rising edge in the other of the first and second inverter chains.
The output of initial inverter U1N in the first inverter chain is heavily loaded by coupling that output to inputs of four additional inverters U3N, U4N, U5N and U6N at node n0, where each of the additional inverters has a drive strength X16 that is approximately at least about 16 times the drive strength X1 of the initial inverter. Similarly, the output of initial inverter U1P in the second inverter chain is heavily loaded by coupling that output to inputs of four additional inverters U3P, U4P, U5P and U6P at node p0, where one again each of the additional inverters has a drive strength X16 that is approximately at least about 16 times the drive strength X1 of the initial inverter. The outputs of the first and second inverter chains are denoted nout and pout, respectively.
The mismatch amplification circuitry 300 further comprises an input circuit 305 configured to generate complementary input signals edgen and edgep for application to respective inputs of the first and second inverter chains. The complementary input signals in the present embodiment have substantially aligned transition times, such that a rising edge of one complementary input signal occurs at substantially the same time as a falling edge of the other complementary input signal, and vice versa. These transition times are substantially aligned regardless of any mismatch between NMOS and PMOS transistors in the input circuit 305.
The input circuit 305 in the present embodiment comprises an input flip-flop UDFF having a data input D driven by a start signal, a clock input driven by a clock signal clk, and a data output Z providing a signal denoted edges. The input circuit 305 further comprises first and second two-input exclusive-or (XOR) gates U0N and U0P each having an input coupled to the data output of the input flip-flop UDFF. The first XOR gate U0N has its other input coupled to an upper supply voltage, illustratively Vdd, and the second XOR gate U0P has its other input coupled to a lower supply voltage, illustratively ground potential. The outputs of the XOR gates U0N and U0P provide the respective complementary input signals edgen and edgep for application to respective inputs of initial inverters U1N and U1P of the first and second inverter chains. As indicated above, inverter chain drive circuits such as XOR gates U0N and U0P in the present embodiment should have similar drive strengths.
The thermometer encoded register 302 comprises input circuitry 310 that includes a first input circuit driven by an output of the first inverter chain and a second input circuit driven by an output of the second inverter chain. The thermometer encoded register 302 further comprises a first bank of flip-flops comprising flip-flops UDN0, UDN1, . . . UDN31 providing respective bits qn[0], qn[1], . . . qn[31] of a first digital output signal, and a second bank of flip-flops comprising flip-flops UDP0, UDP1, . . . UDP31 providing respective bits qp[0], qp[1], . . . qp[31] of a second digital output signal. Although the thermometer encoded register 302 is implemented as a 32-bit register comprising two banks of 32 flip-flops in the present embodiment, registers having a wide variety of other sizes and configurations may be used in other embodiments. Also, although D-type flip-flops are used in this embodiment, other embodiments can utilize other types of flip-flops. The term “flip-flop” as used herein is therefore intended to be broadly construed so as to encompass a wide variety of different types of clocked storage elements.
The first input circuit of the input circuitry 310 comprises a pair of two-input XOR gates UXN0 and UXN1 and generates complementary clock signals clkn and clkp for application to clock inputs of the flip-flops of the respective first and second banks of flip-flops. The second input circuit comprises a pair of two-input XOR gates UXP0 and UXP1 and generates complementary data signals on0 and op0 for application to data inputs of the initial flip-flops UDN0 and UDP0 of the respective first and second banks of flip-flops.
Each of the XOR gates UXN0 and UXN1 receives at one of its inputs the output signal nout from inverter U2N of the first inverter chain. The XOR gate UXN0 has its other input coupled to Vdd, and the XOR gate UXN1 has its other input coupled to ground potential. Similarly, each of the XOR gates UXP0 and UXP1 receives at one of its inputs the output signal pout from inverter U2P of the second inverter chain. The XOR gate UXP0 has its other input coupled to Vdd, and the XOR gate UXP1 has its other input coupled to ground potential.
The thermometer encoded register 302 further includes a differential delay line comprising a plurality of differential delay elements UE0, UE1, . . . UE31 arranged in series with one another. Each differential delay element comprises four inverters, including two series inverters that pass delay element inputs to corresponding Outputs, and a pair of cross-coupled weak inverters configured to balance rise and fall times between the two outputs of the differential delay element. This exemplary differential delay element provides a timing resolution of one inverter delay.
The initial one of the differential delay elements UE0 has first and second inputs coupled to respective outputs of the XOR gates UXP0 and UXP1 and receives the respective complementary data signals on0 and op0 therefrom.
Each of the differential delay elements other than the final one of the differential delay elements UE31 has first and second outputs that are coupled to respective data inputs of corresponding flip-flops in the first and second banks of flip-flops. Thus, for example, the first differential delay element UE0 has data outputs on1 and op1 that are coupled to respective data inputs of flip-flops UDN1 and UDP1 and to respective data inputs of the next differential delay element UE1. Similarly, the second differential delay element UE1 has data outputs on2 and op2 that are coupled to respective data inputs of flip-flops UDN2 and UDP2 and to respective data inputs of the next differential delay element UE2, and so on through the differential delay line.
This exemplary arrangement creates a race condition between the clock signal clkp and the data signals on0, on1, . . . on31 of the first bank of flip-flops UDN0 through UDN31 that controls the respective bits qn[0], qn[1], . . . qn[31] of the first digital output signal, and a race condition between the clock signal clkn and the data signals op0, op1, . . . op31 of the second bank of flip-flops UDP0 through UDP31 that controls the respective bits qp[0], qp[1], . . . qp[31] of the second digital output signal.
As noted above, the digital output signals comprising data outputs of the flip-flops of the first and second banks of flip-flops in the thermometer encoded register 302 are indicative of an amount of mismatch between transistors of different conductivity types in the first and second inverter chains.
The transistors of the first and second conductivity types in the present embodiment may be assumed to comprise respective NMOS and PMOS transistors. A given one of the digital output signals has a first value indicative of an approximate match in speed between the NMOS and PMOS transistors. The digital output signal having a value less than the first value indicates that the NMOS transistors are slower than the PMOS transistors and the digital output signal having a value greater than the first value indicates that the NMOS transistors are faster than the PMOS transistors. Alternatively, the digital output signal having a value less than the first value may indicate that the PMOS transistors are slower than the NMOS transistors and the digital output signal having a value greater than the first value may indicate that the PMOS transistors are faster than the NMOS transistors. The digital output signals may be similarly utilized to indicate differences in drive strength or other characteristics between the NMOS and PMOS transistors.
It should be noted in this regard that the speed of an NMOS or PMOS transistor is closely related to its drive strength. Thus, embodiments described herein with reference to sensing mismatch between NMOS and PMOS transistor speed may be understood to also be indicative of mismatches between NMOS and PMOS drive strength.
In the
The outputs qp[31:0] are the Z outputs of rising edge triggered flip-flops UDP[31:0]. The 0→1 transitions at the respective CLK inputs of UDP[31:0] are caused by a corresponding 0→1 transition on n0, which is caused by the PMOS transistors of inverter U1N. When n0 experiences a 0→1 transition, p0 experiences a 1→0 transition, which is caused by the NMOS transistors of inverter U1P. The 1→0 transition on p0 causes a 0→1 transition on the D input of UDP0 and one of the inputs of UE0. The delay line formed by UE[31:0] “propagates” the transition edges down its length. Accordingly, the PMOS-derived CLK edges cause UDP[31:0] to latch NMOS-derived D inputs.
The outputs qn[31:0] are the Z outputs of rising edge triggered flip-flops UDN[31:0]. The 0→1 transitions at the respective CLK inputs of UDN[31:0] are caused by a corresponding 1→0 transition on n0, which is caused by the NMOS transistors of inverter U1N. When n0 experiences a 1→0 transition, p0 experiences a 0→1 transition, which is caused by the PMOS transistors of inverter U1P. The 0→1 transition on p0 causes a 0→1 transition on the D input of UDN0 and one of the inputs of UE0. The delay line formed by UE[31:0] “propagates” the transition edges down its length. Accordingly, the NMOS-derived CLK edges cause UDN[31:0] to latch PMOS-derived D inputs.
Under an exemplary targeted nominal condition, which may correspond to substantially no mismatch between the NMOS and PMOS transistors of the inverter chains, the outputs qp[31:0] and qn[31:0] are both at the same targeted nominal value, assumed for this example to be 0x00007FFF, which is in hexadecimal notation.
If the PMOS transistors are faster than the targeted nominal and the NMOS transistors are slower than the targeted nominal, the output qp[31:0] will be below the targeted nominal value and the output qn[31:0] will be above the targeted nominal value. Thus, for example, the output qp[31:0] may be 0x0000007F, and the output qn[31:0] may be 0x007FFFFF. This is because qp[31:0] is generated using PMOS-derived CLK edges to cause UDP[31:0] to latch NMOS-derived D inputs, with the PMOS-derived CLK edges arriving earlier than nominal and the NMOS-derived D inputs arriving later than nominal, and because qn[31:0] is generated using NMOS-derived CLK edges to cause UDN[31:0] to latch PMOS-derived D inputs, with the NMOS-derived CLK edges arriving later than nominal and the PMOS-derived D inputs arriving earlier than nominal.
If the PMOS transistors are slower than the targeted nominal and the NMOS transistors are faster than the targeted nominal, the output qp[31:0] will be above the targeted nominal value and the output qn[31:0] will be below the targeted nominal value. Thus, for example, the output qp[31:0] may be 0x007FFFFF, and the output qn[31:0] may be 0x0000007F. Again, this is because qp[31:0] is generated using PMOS-derived CLK edges to cause UDP[31:0] to latch NMOS-derived D inputs, but now with the PMOS-derived CLK edges arriving later than nominal and the NMOS-derived D inputs arriving earlier than nominal, and because qn[31:0] is generated using NMOS-derived CLK edges to cause UDN[31:0] to latch PMOS-derived D inputs, but now with the NMOS-derived CLK edges arriving earlier than nominal and the PMOS-derived D inputs arriving later than nominal.
The above-described operation of the transistor mismatch sensor 110 of
The
In operation, a pulse is applied to the start signal input of the transistor mismatch sensor 110. On the next rising edge of clk, the pulse appears in the edges signal at the output of flip-flop UDFF. The XOR gates U0N and U0P transform the single-ended signal edges into the differential signals edgen and edgep.
It can be seen from the
The signals edgen and edgep drive the respective initial inverters U1N and U1P of the respective first and second inverter chains. As described previously, the initial inverters U1N and U1P of the respective first and second inverter chains are heavily loaded so as to exaggerate transition timing differences between the transistors of the different conductivity types in the corresponding inverter chains.
Due to the heavy loading of the inverters U1N and U1P, the signals at nodes n0 and p0 have slow rise and fall times that can be used to measure NMOS and PMOS mismatch. For example, when the NMOS transistors are faster than the PMOS transistors, the falling edge rate will be faster than the rising edge rate. Similarly, when the NMOS transistors are slower than the PMOS transistors, the rising edge rate will be faster than the falling edge rate. This translates into a pronounced timing delay between the signals at nodes n0 and p0 at a point where these signals cross a voltage that is midway between the upper and lower supplies, in this case a 50% Vdd point, which is the point midway between Vdd and ground potential. By measuring the timing delay between n0 and p0 one can infer the amount of mismatch that exists between the NMOS and PMOS transistors.
The inverters U2N and U2P provide the respective output signals nout and pout in which normal rising and falling edge rates are restored but the timing delay previously established between n0 and p0 at the 50% Vdd point is preserved. The signal nout is used to provide clock signals for the banks of flip-flops in the 32-bit thermometer encoded register 302, while the signal pout is used to provide data signals for the banks of flip-flops. As noted above, the data signals are sent down the differential delay line comprising the differential delay elements UE0, UE1, . . . UE31.
In each of the banks of flip-flops, the corresponding thermometer encoded output measures how far down the differential delay line the data signal has propagated before it is captured by clocking of the flip-flops. More particularly, the qn[31:0] output of the first bank of flip-flops measures the timing delay between nout rising and pout falling at the 50% Vdd point, and the qp[31:0] output of the second bank of flip-flops measures the timing delay between nout falling and pout rising at the 50% Vdd point.
Accordingly, the timing delays between nout and pout in the present embodiment are measured by establishing race conditions between corresponding clock and data signals via the differential delay line. The timing delays are measured by the number of delay elements UE0, UE1, . . . UE31 that the data signal pulse has passed through before the corresponding clock pulse reaches the clock input of the flip-flops. As mentioned previously, the timing resolution of the circuit in this embodiment is one inverter delay.
The transistor mismatch sensor 110 may be tuned such that when the NMOS and PMOS transistors are matched, the value of both qn[31:0] and qp[31:0] will be close to a designated half value, such as 0x00007FFF+/−1 bit. Such circuit tuning may be accomplished, for example, by delaying the nout signal used to provide clock signals to the banks of flip-flops in a clock delay element, although such an element is omitted from the figure for simplicity and clarity of illustration.
Several different cases of relative NMOS and PMOS transistor mismatch that may arise in the transistor mismatch sensor 110 are illustrated in the timing diagrams of
In the
In the
In the
In the
As indicated previously, the heavily loaded inverter chains in the transistor mismatch sensor 110 in the
Again, when the PMOS and NMOS transistors are matched, the thermometer encoded register output value is approximately at half value. If the NMOS transistors are slower than the PMOS transistors, the thermometer encoded register output value will be less than half value. Conversely, if the NMOS transistors are faster than the PMOS transistors, then the thermometer encoded register will be greater than half value. As mentioned above, the half value in a given embodiment is tuned to a value of 0x00007FFF+/−1 bit, although other values can of course be used in other embodiments.
The transistor mismatch sensor 110 of
It is to be appreciated that the particular testing system, tester and transistor mismatch sensor arrangements shown in
As indicated above, embodiments of the invention may be implemented in the form of integrated circuits. In a given such integrated circuit implementation, identical die are typically formed in a repeated pattern on a surface of a semiconductor wafer. Each die includes at least one transistor mismatch sensor as described herein, and may include other structures or circuits. The individual die are cut or diced from the wafer, then packaged as an integrated circuit. One skilled in the art would know how to dice wafers and package die to produce integrated circuits. Integrated circuits so manufactured are considered embodiments of this invention.
It should once again be emphasized that the embodiments of the invention as described herein are intended to be illustrative only. For example, other embodiments of the invention can be implemented using a wide variety of different types of logic gates and other circuitry, providing different configurations of mismatch amplification circuitry and associated registers. Also, different input and output signaling arrangements may be utilized. These and numerous other alternative embodiments within the scope of the following claims will be readily apparent to those skilled in the art.
