Scott Huss

Person

Cary, NC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Reference voltage training scheme
- Patent number 11,580,048
- Issue date Feb 14, 2023
- Cadence Designs Systems, Inc.
- Thomas E. Wilson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transmitter test with interpolation
- Patent number 11,238,204
- Issue date Feb 1, 2022
- Cadence Design Systems, Inc.
- Scott David Huss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock calibration for data serializer
- Patent number 11,228,416
- Issue date Jan 18, 2022
- Cadence Design Systems, Inc.
- Scott David Huss
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data alignment in physical layer device
- Patent number 11,190,331
- Issue date Nov 30, 2021
- Cadence Design Systems, Inc.
- Loren B. Reiss
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dual path level shifter to reduce duty cycle distortion
- Patent number 11,190,189
- Issue date Nov 30, 2021
- Cadence Design Systems, Inc.
- Scott David Huss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static clock calibration in physical layer device
- Patent number 11,165,553
- Issue date Nov 2, 2021
- Cadence Design Systems, Inc.
- Loren B. Reiss
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Transmitter test using phase-lock loop
- Patent number 11,165,554
- Issue date Nov 2, 2021
- Cadence Design Systems, Inc.
- Scott David Huss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase interpolator with phase adjuster for step resolution
- Patent number 11,133,793
- Issue date Sep 28, 2021
- Cadence Design Systems, Inc.
- Scott David Huss
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pause control for a calibration sequence
- Patent number 11,108,425
- Issue date Aug 31, 2021
- Cadence Design Systems, Inc.
- Scott David Huss
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Continuous time linear receiver that minimizes intersymbol interfer...
- Patent number 10,367,661
- Issue date Jul 30, 2019
- Cadence Design Systems, Inc.
- Scott David Huss
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Adaptive pattern filtering for clock and data recovery to minimize...
- Patent number 10,355,889
- Issue date Jul 16, 2019
- Cadence Design Systems, Inc.
- Scott David Huss
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Transconductor circuit for a fourth order PLL
- Patent number 10,153,774
- Issue date Dec 11, 2018
- Cadence Design Systems, Inc.
- Scott David Huss
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low supply current mirror
- Patent number 10,133,292
- Issue date Nov 20, 2018
- Cadence Design Systems, Inc.
- Mark Alan Summers
- G05 - CONTROLLING REGULATING
Information Patent Grant
Method for preventing mis-equalizations in decision feedback equali...
- Patent number 10,069,656
- Issue date Sep 4, 2018
- Cadence Design Systems, Inc.
- Scott David Huss
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method of adaptively controlling a low frequency equalizer
- Patent number 9,998,303
- Issue date Jun 12, 2018
- Cadence Design Systems, Inc.
- Scott David Huss
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method of adaptively controlling the pre-cursor coefficient in a tr...
- Patent number 9,819,520
- Issue date Nov 14, 2017
- Cadence Design Systems, Inc.
- Scott David Huss
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for phase recovery with selective mitigation of t...
- Patent number 9,160,582
- Issue date Oct 13, 2015
- Cadence Design Systems, Inc.
- Scott Huss
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock recovery circuit with second order digital filter
- Patent number 7,127,017
- Issue date Oct 24, 2006
- Rambus, Inc.
- William P. Evans
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Person

Patents Grantslast 30 patents

Reference voltage training scheme

Transmitter test with interpolation

Clock calibration for data serializer

Data alignment in physical layer device

Dual path level shifter to reduce duty cycle distortion

Static clock calibration in physical layer device

Transmitter test using phase-lock loop

Phase interpolator with phase adjuster for step resolution

Pause control for a calibration sequence

Continuous time linear receiver that minimizes intersymbol interfer...

Adaptive pattern filtering for clock and data recovery to minimize...

Transconductor circuit for a fourth order PLL

Low supply current mirror

Method for preventing mis-equalizations in decision feedback equali...

Method of adaptively controlling a low frequency equalizer

Method of adaptively controlling the pre-cursor coefficient in a tr...

System and method for phase recovery with selective mitigation of t...

Clock recovery circuit with second order digital filter