SCOTT K. POZDER

Person

AUSTIN, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
3-D semiconductor die structure with containing feature and method
- Patent number 8,581,383
- Issue date Nov 12, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3-D semiconductor die structure with containing feature and method
- Patent number 7,811,932
- Issue date Oct 12, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of three dimensional integrated circuit employing multi...
- Patent number 7,622,313
- Issue date Nov 24, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Robert E. Jones
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mechanical integrity evaluation of low-k devices with bump shear
- Patent number 7,622,309
- Issue date Nov 24, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Peng Su
- G01 - MEASURING TESTING
Information Patent Grant
Method of forming crack arrest features in embedded device build-up...
- Patent number 7,553,753
- Issue date Jun 30, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Jie-Hua Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having a fuse and method of forming thereof
- Patent number 7,535,078
- Issue date May 19, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Thomas S. Kobayashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Barrier for use in 3-D integration of circuits
- Patent number 7,378,339
- Issue date May 27, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor stacked die/wafer configuration and packaging and met...
- Patent number 7,358,616
- Issue date Apr 15, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Syed M. Alam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die level metal density gradient for improved flip chip package rel...
- Patent number 7,276,435
- Issue date Oct 2, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit having structural support for a flip-chip interc...
- Patent number 7,247,552
- Issue date Jul 24, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a bond pad interface
- Patent number 7,169,694
- Issue date Jan 30, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with magnetically permeable heat sink
- Patent number 7,153,726
- Issue date Dec 26, 2006
- FREESCALE SEMICONDUCTOR, INC.
- Scott K. Pozder
- G11 - INFORMATION STORAGE
Information Patent Grant
Separately strained N-channel and P-channel transistors
- Patent number 7,041,576
- Issue date May 9, 2006
- FREESCALE SEMICONDUCTOR, INC.
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with magnetically permeable heat sink
- Patent number 6,958,548
- Issue date Oct 25, 2005
- FREESCALE SEMICONDUCTOR, INC.
- Scott K. Pozder
- G11 - INFORMATION STORAGE
Information Patent Grant
Metal reduction in wafer scribe area
- Patent number 6,951,801
- Issue date Oct 4, 2005
- FREESCALE SEMICONDUCTOR, INC.
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a semiconductor device having a mechanically rob...
- Patent number 6,803,302
- Issue date Oct 12, 2004
- FREESCALE SEMICONDUCTOR, INC.
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a bond pad and structure thereof
- Patent number 6,531,384
- Issue date Mar 11, 2003
- Motorola, Inc.
- Thomas S. Kobayashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for manufacturing an interconnect structure
- Patent number 6,429,531
- Issue date Aug 6, 2002
- Motorola, Inc.
- Addi B. Mistry
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an alternative ground contact for a semiconductor...
- Patent number 6,420,208
- Issue date Jul 16, 2002
- Motorola, Inc.
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device adhesive layer structure and process for formi...
- Patent number 6,294,458
- Issue date Sep 25, 2001
- Motorola, Inc.
- Jiming Zhang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
3-D SEMICONDUCTOR DIE STRUCTURE WITH CONTAINING FEATURE AND METHOD
- Publication number 20100327440
- Publication date Dec 30, 2010
- FREESCALE SEMICONDUCTOR, INC.
- SCOTT K. POZDER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3-D SEMICONDUCTOR DIE STRUCTURE WITH CONTAINING FEATURE AND METHOD
- Publication number 20090166888
- Publication date Jul 2, 2009
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BARRIER FOR USE IN 3-D INTEGRATION OF CIRCUITS
- Publication number 20080197497
- Publication date Aug 21, 2008
- FREESCALE SEMICONDUCTOR, INC.
- SCOTT K. POZDER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING CRACK ARREST FEATURES IN EMBEDDED DEVICE BUILD-UP...
- Publication number 20080057696
- Publication date Mar 6, 2008
- Jie-Hua Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device having a fuse and method of forming thereof
- Publication number 20070267651
- Publication date Nov 22, 2007
- Thomas S. Kobayashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BARRIER FOR USE IN 3-D INTEGRATION OF CIRCUITS
- Publication number 20070231950
- Publication date Oct 4, 2007
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Magnetic alignment of integrated circuits to each other
- Publication number 20070181653
- Publication date Aug 9, 2007
- Lynne M. Michaelson
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
Semiconductor stacked die/wafer configuration and packaging and met...
- Publication number 20070057384
- Publication date Mar 15, 2007
- Syed M. Alam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fabrication of three dimensional integrated circuit employing multi...
- Publication number 20070023121
- Publication date Feb 1, 2007
- Freescale Semiconductor, Inc.
- Robert E. Jones
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Mechanical integrity evaluation of low-k devices with bump shear
- Publication number 20060292711
- Publication date Dec 28, 2006
- Peng Su
- G01 - MEASURING TESTING
Information Patent Application
Integrated circuit having structural support for a flip-chip interc...
- Publication number 20060154470
- Publication date Jul 13, 2006
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device with magnetically permeable heat sink
- Publication number 20050285259
- Publication date Dec 29, 2005
- Scott K. Pozder
- G11 - INFORMATION STORAGE
Information Patent Application
Backside body contact
- Publication number 20050280088
- Publication date Dec 22, 2005
- Byoung W. Min
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Separately strained N-channel and P-channel transistors
- Publication number 20050275017
- Publication date Dec 15, 2005
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device with magnetically permeable heat sink
- Publication number 20050104193
- Publication date May 19, 2005
- Scott K. Pozder
- G11 - INFORMATION STORAGE
Information Patent Application
Method for forming a bond pad interface
- Publication number 20050014356
- Publication date Jan 20, 2005
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Metal reduction in wafer scribe area
- Publication number 20040147097
- Publication date Jul 29, 2004
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device having a fuse and method of forming thereof
- Publication number 20030151060
- Publication date Aug 14, 2003
- Thomas S. Kobayashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A BOND PAD AND STRUCTURE THEREOF
- Publication number 20030054626
- Publication date Mar 20, 2003
- Thomas S. Kobayashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming a semiconductor device having a mechanically rob...
- Publication number 20010051426
- Publication date Dec 13, 2001
- SCOTT K. POZDER
- H01 - BASIC ELECTRIC ELEMENTS

SCOTT K. POZDER

Person

Patents Grantslast 30 patents

3-D semiconductor die structure with containing feature and method

3-D semiconductor die structure with containing feature and method

Fabrication of three dimensional integrated circuit employing multi...

Mechanical integrity evaluation of low-k devices with bump shear

Method of forming crack arrest features in embedded device build-up...

Semiconductor device having a fuse and method of forming thereof

Barrier for use in 3-D integration of circuits

Semiconductor stacked die/wafer configuration and packaging and met...

Die level metal density gradient for improved flip chip package rel...

Integrated circuit having structural support for a flip-chip interc...

Method for forming a bond pad interface

Semiconductor device with magnetically permeable heat sink

Separately strained N-channel and P-channel transistors

Semiconductor device with magnetically permeable heat sink

Metal reduction in wafer scribe area

Method for forming a semiconductor device having a mechanically rob...

Method of forming a bond pad and structure thereof

Method and apparatus for manufacturing an interconnect structure

Method of forming an alternative ground contact for a semiconductor...

Semiconductor device adhesive layer structure and process for formi...

Patents Applicationslast 30 patents

3-D SEMICONDUCTOR DIE STRUCTURE WITH CONTAINING FEATURE AND METHOD

3-D SEMICONDUCTOR DIE STRUCTURE WITH CONTAINING FEATURE AND METHOD

BARRIER FOR USE IN 3-D INTEGRATION OF CIRCUITS

METHOD OF FORMING CRACK ARREST FEATURES IN EMBEDDED DEVICE BUILD-UP...

Semiconductor device having a fuse and method of forming thereof

BARRIER FOR USE IN 3-D INTEGRATION OF CIRCUITS

Magnetic alignment of integrated circuits to each other

Semiconductor stacked die/wafer configuration and packaging and met...

Fabrication of three dimensional integrated circuit employing multi...

Mechanical integrity evaluation of low-k devices with bump shear

Integrated circuit having structural support for a flip-chip interc...

Semiconductor device with magnetically permeable heat sink

Backside body contact

Separately strained N-channel and P-channel transistors

Semiconductor device with magnetically permeable heat sink

Method for forming a bond pad interface

Metal reduction in wafer scribe area

Semiconductor device having a fuse and method of forming thereof

METHOD OF FORMING A BOND PAD AND STRUCTURE THEREOF

Method for forming a semiconductor device having a mechanically rob...