Patent Application
20050280088
1. Field of the Invention
This invention relates in general to semiconductor devices and in particular to a backside body contact.
2. Description of the Related Art
With some integrated circuits, it may be important to bias the body of a transistor. For example, with some transistors, it may be desirable to ground the body. With other transistors, it may be beneficial to change the body bias during operation e.g. such as for transistors used in memory arrays or other transistors where it is desirable to change the threshold voltage during operation. Still with other transistors (e.g. transistors having a semiconductor on insulator (SOI) configuration), biasing the body may reduce a transient circuit effect from a floating body voltage.
What is desirable is a new way to bias the body of a transistor.
The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The figures are not necessarily drawn to scale.
The following sets forth a detailed description of a mode for carrying out the invention. The description is intended to be illustrative of the invention and should not be taken to be limiting.
In the embodiment shown, active region 106 includes two source/drain regions 111 and 113 and a body region 109 located there between. In the embodiment shown, source/drain regions 111 and 113 are doped to be a first conductivity type (e.g. N-type or P-type) and body 109 is doped to be of a second conductivity type (the other of N-type or P-type). Body 109 includes a channel region located beneath gate 117.
A gate/contact layer 108 is locate over active layer 107. Gate/contact layer includes gates (e.g. gate 117 of transistor 115), source/drain contacts (e.g. source/drain contacts 121 and 119 of transistor 115) and gate contacts (e.g. gate contact 118 of transistor 115) of transistors having their active regions in layer 107. Layer 108 also includes dielectric material for desired electrical isolation of the conductive structures of layer 108 and adjacent layers. The gates (e.g. 117) and source/drain regions (e.g. 111 and 113) may include silicided portions (not shown) contacting its respective gate or source/drain contact.
A metal 1 interconnect layer 123 is located over layer 108. Layer 125 represents one or more additional metal interconnect layers (e.g. metal interconnect layers 2-9 in one embodiment) located over layer 108. The metal interconnect layers in layer 123 and layer 125 include metal interconnects (e.g. 134) and vias (not shown in layers 123 and 125 of
In the embodiment shown, layer 123 includes an interconnect 133 coupled to a body bias source (not shown). In one embodiment, the body bias source is coupled to a supply voltage (e.g. at a ground or non ground voltage). In other embodiments, the voltage of the body bias source may be varied during operation to bias body 109 at different voltages during operation.
Referring to
In other embodiments, openings 401 and 501 are formed with the same mask and etching. However, forming them separately may, in some embodiments, reduce the crystal damage to active region 106.
Referring to
In some embodiments, a dopant of the same conductivity type as body 109 may be implanted into body 109 before or after forming sidewall spacer 601 to ensure that the conductive material in opening 501 does not contact a source/drain region of transistor 115. Thus, if opening 501 were to become misaligned and expose a portion of source/drain region 111 or region 113, then the dopant from this doping would transform that portion of the source/drain region to a portion of the body of the transistor.
In one embodiment, a layer (or layers) of barrier material is deposited (e.g. by chemical vapor deposition (CVD) or by physical vapor deposition) over wafer 101 including in openings 401 and 501 wherein the layer of barrier material physically contacts interconnect 133 and body 109. In some embodiments, a silicide (not shown) of e.g. of cobalt or nickel may be formed on body 109 prior to the deposition of the barrier material. A layer of conductive fill material is then deposited over the layer of barrier material, wherein the back side of wafer 101 is subject to a chemical mechanical polish (CMP) using layer 105 as a polishing stop. The conductive structure in openings 401 and 501 maybe formed by other techniques and/or may be made of other materials in other embodiments. In some embodiments, the openings may not include a barrier layer.
In some embodiments, other metal interconnect layers (not shown) maybe formed over metal interconnect layer 801. These other metal interconnect layers may include metal interconnects and vias coupled to transistors having active regions in layer 107. With some of these embodiments, other conductive structures may extend through layer 105. In some embodiments, external connectors or bond pads may be formed on the back side of wafer 101 over layer 801. In one embodiment, interconnect 803 may be coupled to the body of other transistors.
In some embodiments, other metal interconnect layers maybe formed over layer 125 after substrate 201 has been removed.
Other processing steps may be performed on wafer 101 subsequent to the view shown in
In some embodiments, providing a conductive structure in electrical contact with the body through the insulating layer may reduce the area needed for biasing the body of a transistor. Consequently, with some embodiments, additional active area outside of the gate and source drain regions of a transistor is not needed for body biasing.
In other embodiments, opening 501 in layer 105 may be formed at other times in the processing of wafer 101. For example, opening 501 may be formed after forming gate 117 (and forming the source/drain silicides and gate silicides) but prior to forming source/drain contacts 121 and 119 and prior to forming gate contact 118. Remaining structures of layer 108 and layers 123 and 125 would be formed after the removal substrate 201. With other embodiments, opening 501 may be formed prior to the formation of gate 117. In some embodiments, opening 501 may be formed prior to the formation of layer 123 but after the formation of layer 108. In one embodiment where the gate is formed before the body contact, the high temperature processing to form the transistor including the gate is first performed before the metal of interconnect 803 is formed. In some embodiments, some of the metal interconnect layers of layer 125 may be formed prior to forming opening 501, with the other metal interconnect layers being formed after the removal of substrate 201.
In other embodiments, polysilicon may be used to fill opening 501 and for interconnect 803. In such embodiments, after the formation of spacers 601 and 603 (see
In other embodiments, the transistors having their active regions in layer 107 may be bonded to another wafer having a second active layer with active regions for other transistors. With such embodiments, the resultant integrated circuit would have multiple active layers. The openings to the bodies of the transistors maybe formed prior to or subsequent to the bonding of the second wafer. In some embodiments, interconnect 803 is coupled to a body bias source located on the backside of wafer 101.
In one embodiment of the invention, a semiconductor device includes an active region including a body, a first source/drain region, and a second source/drain region of a transistor. The semiconductor device includes a gate of the transistor. The gate is located adjacent to the body with respect to a first side of the active region. The semiconductor device also includes an insulating layer located with respect to a second side of the active region. The active region is between the insulating layer and the gate. The semiconductor device also includes an opening through the insulating layer and a conductive structure in electrical contact with the body through the opening.
In another embodiment of the invention, a semiconductor device includes an active layer including an active region, a first source/drain region in the active region, and a second source/drain region in the active region. The semiconductor device also includes a body in the active region. The body is located between the first source/drain region and the second source/drain region. The semiconductor device also includes a gate adjacent to the body with respect to a first side of the active layer and an insulating layer adjacent to the body with respect to a second side of the active layer. The semiconductor device also includes a first opening through the insulating layer adjacent to the body and a first conductive structure in the first opening in electrical contact with the body.
In another embodiment of the invention, a method of making a semiconductor device includes forming a first layer with an active region. The active region includes a body of a transistor. The method also includes forming a gate located with respect to a first side of the first layer and forming an opening through an insulating layer adjacent to the body. The insulating layer is located with respect to a second side of the first layer. The method further includes forming conductive material in the opening.
In another embodiment of the invention, a method of making a semiconductor device includes providing a first layer having a first side and a second side and an insulating layer located with respect to the second side. The insulating layer is located between the first layer and a first substrate layer. The first layer including an active region with a transistor body. The method also includes forming a gate of a transistor located with respect to the first side of the first layer and forming a second substrate layer located with respect to the first side of the first layer. The method further includes removing the first substrate layer subsequent to the forming the second substrate layer, forming an opening through the insulating layer after the removing the first substrate layer, and forming conductive material in the opening. The conductive material is in electrical contact with the body.
While particular embodiments of the present invention have been shown and described, it will be recognized to those skilled in the art that, based upon the teachings herein, further changes and modifications may be made without departing from this invention and its broader aspects, and thus, the appended claims are to encompass within their scope all such changes and modifications as are within the true spirit and scope of this invention.
