Sean G. Gibb

Person

Calgary, CA

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for mitigating effects of hash collisions in hard...
- Patent number 11,804,852
- Issue date Oct 31, 2023
- Eidetic Communications Inc.
- Saeed Fouladi Fard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for controlling a computational storage processor
- Patent number 11,687,365
- Issue date Jun 27, 2023
- Eidetic Communications Inc.
- Sean Gregory Gibb
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for controlling data acceleration
- Patent number 10,996,892
- Issue date May 4, 2021
- Eidetic Communications Inc.
- Sean Gibb
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for estimating an expectation of forward error co...
- Patent number 9,793,924
- Issue date Oct 17, 2017
- Microsemi Solutions (U.S.), Inc.
- Peter Graumann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for boost floor mitigation
- Patent number 9,602,133
- Issue date Mar 21, 2017
- Microsemi Storage Solutions (U.S.), Inc.
- Peter Graumann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and system for forward error correction decoding based on a...
- Patent number 9,564,921
- Issue date Feb 7, 2017
- Microsemi Storage Solutions (U.S.), Inc.
- Peter Graumann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Error correction code decoder with stochastic floor mitigation
- Patent number 9,564,922
- Issue date Feb 7, 2017
- Microsemi Storage Solutions (U.S.), Inc.
- Peter Graumann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Forward error correction decoder system
- Patent number 9,473,175
- Issue date Oct 18, 2016
- Microsemi Storage Solutions (U.S.), Inc.
- Peter Graumann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Forward error correction decoder and method therefor
- Patent number 9,467,172
- Issue date Oct 11, 2016
- Microsemi Storage Solutions (U.S.), Inc.
- Peter Graumann
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed LDPC decoder
- Patent number 9,432,053
- Issue date Aug 30, 2016
- Microsemi Storage Solutions (U.S.), Inc.
- Peter Graumann
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Forward error correction decoder and method therefor
- Patent number 9,325,347
- Issue date Apr 26, 2016
- Microsemi Storage Solutions (U.S.), Inc.
- Peter Graumann
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for decoding encoded data stored in a non-volatil...
- Patent number 9,170,876
- Issue date Oct 27, 2015
- PMC-Sierra US, Inc.
- Stephen Bates
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed gain and phase recovery in presence of phase noise
- Patent number 8,938,037
- Issue date Jan 20, 2015
- PMC-Sierra US, Inc.
- Saeed Fard
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Forward error correction with extended effective block size
- Patent number 8,631,309
- Issue date Jan 14, 2014
- PMC-Sierra, Inc.
- Peter Graumann
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipelined FFT processor with memory address interleaving
- Patent number 7,428,564
- Issue date Sep 23, 2008
- Sean G. Gibb
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interleaving input sequences to memory
- Patent number 7,415,584
- Issue date Aug 19, 2008
- Cygnus Communications Canada Co.
- Sean G. Gibb
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ROUTING DATA BETWEEN PROCESSING UNITS INDENTIFIED BY A SEQUENTIALLY...
- Publication number 20230359581
- Publication date Nov 9, 2023
- Eidetic Communications Inc.
- Sean Gregory GIBB
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR MITIGATING EFFECTS OF HASH COLLISIONS IN HARD...
- Publication number 20230060654
- Publication date Mar 2, 2023
- Eidetic Communications Inc.
- Saeed Fouladi Fard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CONTROLLING A COMPUTATIONAL STORAGE PROCESSOR
- Publication number 20220197704
- Publication date Jun 23, 2022
- Eidetic Communications Inc.
- Sean Gregory GIBB
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR CONTROLLING DATA ACCELERATION
- Publication number 20200050401
- Publication date Feb 13, 2020
- Eidetic Communications Inc.
- Sean GIBB
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR TCP OFFLOAD FOR NVME OVER TCP-IP
- Publication number 20190163364
- Publication date May 30, 2019
- Eidetic Communications Inc.
- Sean GIBB
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FORWARD ERROR CORRECTION WITH EXTENDED EFFECTIVE BLOCK SIZE
- Publication number 20120300873
- Publication date Nov 29, 2012
- PMC-Sierra, Inc.
- Peter Graumann
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PIPELINED FFT PROCESSOR WITH MEMORY ADDRESS INTERLEAVING
- Publication number 20080288569
- Publication date Nov 20, 2008
- CYGNUS COMMUNICATIONS CANADA CO.
- Sean G. Gibb
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interleaving memory
- Publication number 20050114421
- Publication date May 26, 2005
- Sean G. Gibb
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pipelined FFT processor with memory address interleaving
- Publication number 20050114420
- Publication date May 26, 2005
- Sean G. Gibb
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Recoded radix-2 pipeline FFT processor
- Publication number 20050015420
- Publication date Jan 20, 2005
- Sean G. Gibb
- G06 - COMPUTING CALCULATING COUNTING

Sean G. Gibb

Person

Patents Grantslast 30 patents

System and method for mitigating effects of hash collisions in hard...

Method and apparatus for controlling a computational storage processor

Apparatus and method for controlling data acceleration

Method and system for estimating an expectation of forward error co...

System and method for boost floor mitigation

Method and system for forward error correction decoding based on a...

Error correction code decoder with stochastic floor mitigation

Forward error correction decoder system

Forward error correction decoder and method therefor

High speed LDPC decoder

Forward error correction decoder and method therefor

Method and system for decoding encoded data stored in a non-volatil...

High speed gain and phase recovery in presence of phase noise

Forward error correction with extended effective block size

Pipelined FFT processor with memory address interleaving

Interleaving input sequences to memory

Patents Applicationslast 30 patents

ROUTING DATA BETWEEN PROCESSING UNITS INDENTIFIED BY A SEQUENTIALLY...

SYSTEM AND METHOD FOR MITIGATING EFFECTS OF HASH COLLISIONS IN HARD...

METHOD AND APPARATUS FOR CONTROLLING A COMPUTATIONAL STORAGE PROCESSOR

APPARATUS AND METHOD FOR CONTROLLING DATA ACCELERATION

SYSTEM AND METHOD FOR TCP OFFLOAD FOR NVME OVER TCP-IP

FORWARD ERROR CORRECTION WITH EXTENDED EFFECTIVE BLOCK SIZE

PIPELINED FFT PROCESSOR WITH MEMORY ADDRESS INTERLEAVING

Interleaving memory

Pipelined FFT processor with memory address interleaving

Recoded radix-2 pipeline FFT processor