Sean Moran

Person

Burlingame, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
2.5D microelectronic assembly and method with circuit structure for...
- Patent number 9,917,042
- Issue date Mar 13, 2018
- Invensas Corporation
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer-level flipped die stacks with leadframes or metal foil interc...
- Patent number 9,666,513
- Issue date May 30, 2017
- Invensas Corporation
- Ashok S. Prabhu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer-level flipped die stacks with leadframes or metal foil interc...
- Patent number 9,490,195
- Issue date Nov 8, 2016
- Invensas Corporation
- Ashok S. Prabhu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic package
- Patent number 9,349,672
- Issue date May 24, 2016
- Tessera, Inc.
- Ilyas Mohammed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnection element with posts formed by plating
- Patent number 9,282,640
- Issue date Mar 8, 2016
- Tessera, Inc.
- Jinsu Kwon
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of fabricating an interconnection element having conductive...
- Patent number 8,505,199
- Issue date Aug 13, 2013
- Tessera, Inc.
- Jinsu Kwon
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Microelectronic package
- Patent number 8,299,626
- Issue date Oct 30, 2012
- Tessera, Inc.
- Ilyas Mohammed
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
WAFER-LEVEL FLIPPED DIE STACKS WITH LEADFRAMES OR METAL FOIL INTERC...
- Publication number 20170077016
- Publication date Mar 16, 2017
- Invensas Corporation
- Ashok S. Prabhu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NEW 2.5D MICROELECTRONIC ASSEMBLY AND METHOD WITH CIRCUIT STRUCTURE...
- Publication number 20160329300
- Publication date Nov 10, 2016
- Invensas Corporation
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECTION ELEMENT WITH POSTS FORMED BY PLATING
- Publication number 20130286619
- Publication date Oct 31, 2013
- Jinsu Kwon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC PACKAGE
- Publication number 20130249116
- Publication date Sep 26, 2013
- Tessera, Inc.
- Ilyas Mohammed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interconnection element with posts formed by plating
- Publication number 20090145645
- Publication date Jun 11, 2009
- Tessera, Inc.
- Jinsu Kwon
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Interconnection element with plated posts formed on mandrel
- Publication number 20090148594
- Publication date Jun 11, 2009
- Tessera, Inc.
- Sean Moran
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Multilayer substrate with interconnection vias and method of manufa...
- Publication number 20090071707
- Publication date Mar 19, 2009
- Tessera, Inc.
- Kimitaka Endo
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
Microelectronic package
- Publication number 20090045524
- Publication date Feb 19, 2009
- Tessera, Inc.
- IIyas Mohammed
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

2.5D microelectronic assembly and method with circuit structure for...

Wafer-level flipped die stacks with leadframes or metal foil interc...

Wafer-level flipped die stacks with leadframes or metal foil interc...

Microelectronic package

Interconnection element with posts formed by plating

Method of fabricating an interconnection element having conductive...

Microelectronic package

Patents Applicationslast 30 patents

WAFER-LEVEL FLIPPED DIE STACKS WITH LEADFRAMES OR METAL FOIL INTERC...

NEW 2.5D MICROELECTRONIC ASSEMBLY AND METHOD WITH CIRCUIT STRUCTURE...

INTERCONNECTION ELEMENT WITH POSTS FORMED BY PLATING

MICROELECTRONIC PACKAGE

Interconnection element with posts formed by plating

Interconnection element with plated posts formed on mandrel

Multilayer substrate with interconnection vias and method of manufa...

Microelectronic package