The subject matter of the present application relates to a multi-layer substrate, wiring board, or interconnection element, including vias that provide electrical interconnection between layers, for example, and a method of manufacturing such multilayer substrate, wiring board, or interconnection element.
Multilayer substrates are commonly used for interconnection, support, or integration of electronic devices such as microchips, SAW filters, etc., which may be pre-packaged or may be combined with the multilayer substrate in a package. The multilayer substrates include conductive layers with traces, wirings, pads, etc, on both sides of an insulating layer. The conductive layers may be electrically interconnected through the insulating layer to electrically connect signal paths, ground planes, etc or for mechanical connection for improved thermal conduction, improved adherence of the individual layers, etc. Such interconnection is usually done with conductive features called vias. The manufacturing of these substrates has become increasingly complicated in recent years. This is due to the use of electronic devices that are made with smaller footprints and are made for high-density packaging. In addition, communication in electronic devices is becoming increasingly fast. Therefore, communication paths have to be made suitable for high-speed communication. The increase in communication speed requires improved electrical conduction between layers of a multilayer substrate. In addition, smaller sized conduction paths can reduce capacitive and inductive behavior of the conduction paths.
In the case of a multilayer substrate, conductive and non-conductive layers alternate each other. The non-conductive layers are usually made of a dielectric layer that insulates two conducting layers that are arranged on each side of the dielectric layer. The conductive layers are usually patterned to form conductive features such as traces, connections, pads, terminals, etc. For an electrical interconnection of the conductive layers with each other, vias are manufactured into the dielectric layer. Signals, power supply lines, thermal conduction etc. can thereby go from a trace formed from one conductive layer to a trace of the other conductive layer on opposite sides of the dielectric layer. Preferably such vias are made very small to allow a high density of traces, pads, and other conductive features of the multilayer substrate.
Different methods of manufacturing such vias for interconnecting conductive layers have been proposed. In one background method, a patterned circuit layer is covered with a dielectric layer. Via holes are then formed into the dielectric layer that will expose portions of the patterned circuit layer. The via holes are then filled with solder material that adheres to the patterned circuit layer to form an interconnection via. Subsequently, another metal layer is laminated over the solder material that will form the vias, and over the upper surface of the dielectric layer. The laminated metal layer is then brought into electrical connection of the vias made of solder a step of heating to wet the solder of adhesion.
Another method of manufacturing vias in a multilayer substrate was described in the U.S. Pat. No. 5,956,843. In this patent, holes for vias are formed at predetermined positions in a first insulating layer. A first thin metal layer is then deposited into said via holes. Such deposition is done by an electroless CAP plating. The first metal layer is also deposited at areas on top of the insulating layer adjacent to the via hole. A substantial portion of the via hole is thereby still void of any material. Subsequently, the remaining portions of the via holes that are void are filled with a copper paste. The upper surfaces of the first metal layer and the insulating layer are then smoothed after the filling with copper paste by grinding. Additional insulating layers, vias, and metal layers may be added subsequently, to add additional layers to the multilayer substrate.
Another method of manufacturing such vias was described in the U.S. Pat. No. 6,884,709. In this method, a first support layer is prepared with a plurality of posts that project from the surfaces the first support layer. In addition, a second support layer is prepared with an insulating film for interlayer insulation that was deposited on a surface of the second support layer. Holes corresponding to the projecting posts of the first layer are then formed in the insulating film that covers the second layer. In a next step, the first and second support layers are brought face-to-face with each other, so that the projecting posts are aligned with the holes formed in the insulating film. Next, the first and second layers are pressed into each other so as to make the insulating film be penetrated with the projecting posts. Then, the first and second support layers are removed, and an insulating film remains with the posts traversing the insulating film at locations of the holes. The insulating film can then be laminated with metal layers from both sides so as to form two patterned wiring layers that are interconnected with the posts.
Despite all the advancements in technology for manufacturing multilayer substrates, still further improvements in making such substrates would be desirable.
In accordance with an aspect of the invention, a method is provided for manufacturing a multilayer substrate. In such method, an insulating layer can have a hole overlying a patterned second metal layer. In turn, the second metal layer can overlie a first metal layer. A third metal layer can be electroplated onto the patterned second metal layer within the hole, the third metal layer extending from the second metal layer onto a wall of the hole. When plating the third metal layer, the first and second metal layers can function as a conductive commoning element.
In accordance with another aspect of the invention, a method is provided for manufacturing a multilayer substrate. In such method, a via-hole can be formed which extends through a first insulating layer to expose a first patterned metal layer. The first patterned metal layer may overlie and be in conductive communication with a second metal layer. The via hole can then be filled substantially with metal to form a via by electroplating such that the via is in conductive communication with the first patterned metal layer. A third metal layer can be formed at least on top of and in conductive communication with the via. When electroplating the via, the second metal layer can function as a conductive path for an electroplating current.
In accordance with an aspect of the invention, a method is provided for manufacturing a conductive via at least partially within an opening of a non-conductive layer overlying a metallic pad, in which the metallic pad overlies and is in conductive communication with a base metal layer. In such method, the opening can be filled substantially with metal to form a via by electroplating, such that the via is in conductive communication with the metallic pad. When filling the opening by electroplating, the base metal layer and the metallic pad can conduct an electroplating current.
In accordance with another aspect of the invention, a multilayer wiring element is provided which can include a first patterned metal layer having an upper surface and a lower surface remote from the upper surface. An insulating layer can overlie the upper surface of the first patterned metal layer, with the insulating layer having a hole exposing the first patterned metal layer. A plated second metal layer can extend upwardly along a wall of the hole from the first patterned metal layer. A third metal layer can overlie an upper surface of the insulating layer and be in conductive communication with the second metal layer. A metallic post may protrude from the lower surface of the first patterned metal layer.
These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims and accompanying drawings where:
a-1j are diagrammatic cross-sectional views of the stages in method in accordance with a first embodiment of the present invention;
k-1L illustrate stages in a method in accordance with a variation of the first embodiment;
a-e are depicting diagrammatic cross-sectional views of stages in method in accordance with the first embodiment of the present invention;
The above
In a method of manufacturing a multilayer substrate according to a first embodiment of the present invention, a composite metal sheet 10 is provided (
Moreover, as used in this disclosure, a terminal or other conductive feature is regarded as “exposed at” a surface of a dielectric element or solder mask layer where the terminal is arranged so that all or part of the conductive feature can be seen by looking at such surface. Thus, a conductive feature which is exposed at a surface of a dielectric element or solder mask layer may project from such surface; may be flush with such surface; or may be recessed from such surface and exposed through an opening extending entirely or partially through the dielectric element.
A mask 24 is formed over the first metal layer 16 which exposes portions 26 of the first metal layer 16. The second metal layer 12 may also be covered by a mask layer 22 so that the subsequent etching process does not attack the bottom layer 12. (
In a next step, the upper surfaces of the etch stop layer 14 and the patterned first layer 16 are covered with a dielectric layer 42 or other insulating material (
As shown in
As illustrated in
Thereafter, the filling of the holes 50 can be done via electroplating, where the bottom layer 12 and etch-stop layer 14, when present, are used as a conductor for the electroplating current for all pads 36 that are exposed within the via holes 50. The upper surface 32 of pads 36 will be in contact with the electrolyte of the plating bath, and thereby will form the cathode for electroplating. Since the bottom layer 12 is in electrical contact with the upper surfaces 32 of pads 36 by the etch stop layer 14, metal ions can be deposited into holes 50 so as to fill the holes 50 with metal. Multiple vias 52 can thereby be simultaneously formed by a plating process. The electroplating fills holes 50 substantially with metal to build up vias 52 made of a homogenous metal that are in electrical communication with the pads 36, the etch stop layer 14, and the second layer 12. The filling of holes 50 can be continued until the hole 50 is substantially or completely filled.
When filling the via holes, a third metal layer 66 is formed on the exposed surface 46 of the insulating layer 42. After deposition of the third metal layer 66, layer 66 can be patterned, such as by photolithography to form traces 68 and pads 65. The length D1 of the vias 52 may be longer than the thickness D2 of the third metal layer 66 in a particular example of the process. In another example, the thickness of layer 66 is greater. Next, it is also possible to deposit a protective layer (not shown) on top of the upper surface of the third metal layer, for example a thin gold or silver layer for protection purposes.
At this stage in the method of manufacturing a multilayer substrate, it is possible to add additional layers. For example, an additional step of adding a next dielectric layer can be performed as described above with reference to
Next, after forming vias 52 and forming the third metal layer 66, the second metal layer 12 can be processed. A mask 61 (
Since the etch stop layer 14 is still in electrical connection with all of the protrusions 72 and the pads 36, the etch-stop layer 14 is then removed at portions other than the portions covered by protrusion 72 (
Next, the first metal layer 16 and the lower surface 48 of the dielectric layer 42 are covered with a first solder resist layer 82. In addition, the third metal layer 66 and the upper surface 46 of the dielectric layer 42 are preferably covered with a second solder resist layer 84. (
Subsequently, solder resist layer 84 is selectively removed from the upper surface thereof to form holes 86 to expose at least a portion of upper surfaces 62 of the pads 65. The removal may be done by an etching process, or by mechanical removal by grinding, laser drilling, etc. The exposed surfaces 62 of pad 65 form an upper terminal of the finished multilayer substrate 20. (
It is possible to add a protective layer over the exposed surfaces 62 of pads 65. For example a thin gold or silver layer (not shown) may be deposited over these surfaces 62, so as to prevent corrosion. Such layers may also be deposited by an electroplating process, or by other metallic deposition processes.
In a variation of the above embodiment, a semi-additive electroplating process may be used. In this method, the vias 52 and the pads 65 and traces 68 of the third metal layer 66 are defined by the same build-up electroplating process. For this purpose, the portions of the upper surface 46 of the dielectric layer 42, the inner walls 44 of the holes 50, and the exposed surface 32 of pads 36 are covered with a thin metal layer or barrier layer for the electroplating process. The barrier layer may be made from a conductive metal such as copper, tantalum or titanium, etc. The portions 64 (FIG. f) above the dielectric layer, where metal layer 66 should not be deposited, are covered with a mask layer, that is a negative image of the patterns formed by pads 65 and traces 68 of the third conductive layer 66. Subsequently the electroplating process is started, and via holes 50 are filled with metal to form vias 52, and the third metal layer 66 is built up to form the portions of the barrier layer that are not covered by a mask. Thereby, pads 65, traces 68 and other metallic patterns of the third metal layer 66 may be created. Subsequently, the mask that was used to prevent build-up of metal at portions 64 can be removed, for example by a step of etching that does not attack the metal of the third metal layer 66.
Referring to
The stages of the method of manufacturing a multilayer substrate as shown with reference to
a shows a schematic representation of an electroplating apparatus 90 that can be used to perform electroplating of substrate 40. When using electroplating, metal layers can be deposited onto conductive surfaces, and holes may be filled with metal. For example, copper (Cu) films can be deposited onto other conductive surfaces. Other metals may be deposited in the electroplating process, such as nickel (Ni), gold (Au), gold-tin alloys, aluminum (Al), aluminum-copper alloys, tin, silver (Ag) etc. depending on the requirements of the plated layers. Electroplating apparatus 90 includes a DC power source 97 that is connected with the positive pole by a positive electrode (anode) 95 that is located inside an electrolyte solution 92 in a bulk deposition tub 91. The electrolyte solution is preferably a copper sulfate (CuSO4). The negative pole of the power source 97 is connected with to a shaft 98. A chuck 94 is connected to the shaft 98, and the lower surface of the chuck 94 holds the unfinished multilayer substrate 40. It has to be noted that the substrate 40 shown is merely for representation purposes only. In reality, the unfinished substrate 40 will be much wider in x-direction and much thinner in y-direction. In the representation of
The shaft 98, chuck 94, second metal layer 12, and pads 36 of the first metal layer 16 of the unfinished multilayer substrate 40 are in electrical contact with each other, so that the pads 36 form the negative electrode (cathode) for the electroplating process. The surface 32 of the pads 36 of the first metal layer 16 will be in contact with the electrolyte solutions 92. The shaft 98 may be configured to move the chuck 94 up and down the y-axis to place the chuck 94 with the multilayer substrate 40 into and out of the electrolyte solution 92 of the deposition tub 91. In addition, the shaft 98 may be configured to rotate the chuck 94 during the electroplating process. The unfinished multilayer substrate 40 is temporarily attached to the lower surface of chuck 94 by a conductive adhesive 96 that provides homogenous electrical connection between both the lower surface of chuck 94, and the surface of second metal layer 12 of substrate 40. The other portions of chuck 94 may be coated by a non-conductive material such as Teflon, so as to avoid deposition of films on the chuck itself.
When the substrate 40 is held by chuck 94 into electrolyte solution 92, the DC power source 97 is put into electrical contact with the cathodes formed by the surfaces 32 of pads 36 by switch 99. Since switch 99 closes an electrical loop, a current will flow from through the electrolyte 92 from anode 95 to the cathode, formed by surfaces 32. At least a portion of this current will be positively charged metal ions, for example copper ions (Cu++) which will be attracted and will adhere to the surfaces 32 of pads 36. Continuously a metal film will thereby be developed in the via holes 50.
b shows a diagrammatic cross-sectional close-up view of the area A1 shown in
c shows a diagrammatic cross-sectional close-up view of the area A1 shown in
In a variant of filling the hole 50 by a electroplating with metal as shown in
As described above with reference to the fully-additive electroplating process, the barrier layer 57 may also extend to surface 46 of the dielectric layer 42, as shown with reference to
In a variant, the barrier layer 57 is deposited over the entire surface 46 of the dielectric layer 42 of substrate 40, on the side walls 44 of holes 50, and on the exposed surface 32 of pads 36, if the semi-additive electroplating process is used. Thereby, the holes 50 can be filled by electroplating, and after the filling of the holes 50, the third metal layer 66 can be built up over the vias 52 and the dielectric layer 42 (
It is also possible that the seed layer 51 be deposited by a CVD process or PVD (sputtering). In the PVD process, a plasma with positively charged ions are produced that are caused to collide with a metal target, to produce a shower of copper particles on the surface 32 and walls of the via holes. After depositing a seed layer by these alternative methods, the remaining portions of the hole 50 may be filled with an electroplating process to provide a bulk filling layer 53.
The resulting multilayer substrate 20 of the above described method is exemplary only. Other types of multilayer substrates may be manufactured with the same process. For example, another embodiment of the multilayer substrate 120 of the present invention is shown with respect to
Numerous variations and combinations of the features discussed above can be employed. For example, the number of vias, pads and traces, as well as layers of metal and dielectric material can be increased. Electronic devices that may be mounted or connected to multilayer substrates other than packaged chips may be for example, passive components, filters, etc. Further, bonding materials other than solder can be used. As these and other variations and combinations of the features discussed above can be utilized, the foregoing description of the preferred embodiment should be taken by way of illustration rather than by way of limitation of the invention.
This application claims the benefit of the filing date of U.S. Provisional Application No. 60/964,916 filed Aug. 15, 2007, the disclosure of which is hereby incorporated by reference herein.
Number | Date | Country | |
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60964916 | Aug 2007 | US |